diff --git a/ipcore/SPLL/.last_generated b/ipcore/SPLL/.last_generated index ab5d3a1..8ec0a2e 100644 --- a/ipcore/SPLL/.last_generated +++ b/ipcore/SPLL/.last_generated @@ -1,2 +1,2 @@ -2024-01-10 21:58 +2024-01-11 09:39 rev_1 \ No newline at end of file diff --git a/ipcore/SPLL/SPLL.idf b/ipcore/SPLL/SPLL.idf index f266421..e584f38 100644 --- a/ipcore/SPLL/SPLL.idf +++ b/ipcore/SPLL/SPLL.idf @@ -19,106 +19,128 @@ false - CLKOUT0_EXT_EN_advancedPage - false + CLKOUT0_REQ_PHASE_basicPage + 0.0000 + 4 - DYNAMIC_PHASE4_EN_advancedPage + RSTODIV_ENABLE_advancedPage false - CLKSWITCH_FLAG_ENABLE_advancedPage - false + STATIC_RATIOF_basicPage + 24 - FB_MODE_basicPage - 0 + CLKOUT3_REQ_FREQ_basicPage + 50.0000 + 4 - RST_ENABLE_advancedPage + CLKOUT4_REQ_PHASE_basicPage + 0.0000 + 4 + + + CLKOUT1_REQ_DUTY_basicPage + 50.0000 + 4 + + + FEEDBACK_DELAY_ENABLE_advancedPage false - CLKOUT5_EN_advancedPage + DYNAMIC_RATIO0_EN_advancedPage false - DEVICE_PGL22 - true + DYNAMIC_CLKIN_EN_basicPage + false - CLKOUT3_REQ_FREQ_basicPage - 50.0000 - 4 + CLKOUT0_EN_basicPage + true - CLKOUT1_EN_advancedPage + DYNAMIC_PHASE0_EN_advancedPage false - CLK_CAS3_EN_advancedPage - false + STATIC_RATIO2_advancedPage + 16 - CLKOUT0_REQ_DUTY_basicPage - 50.0000 - 4 + CLKOUT3_EN_basicPage + false - DYNAMIC_CLKIN_EN_basicPage + LOOP_MAPPING_EN_advancedPage false - STATIC_PHASE4_advancedPage + STATIC_PHASE3_basicPage 16 - STATIC_RATIO0_basicPage + STATIC_DUTY0_basicPage 24 - STATIC_PHASE0_advancedPage + STATIC_RATIOM_advancedPage + 1 + + + CLKOUT2_EN_basicPage + true + + + STATIC_DUTY0_advancedPage 16 - FBMODE_basicPage + PFDEN_EN_advancedPage false - FEEDBACK_DELAY_ENABLE_advancedPage - false + FBDIV_SEL_basicPage + 0 - DYNAMIC_DUTY1_EN_advancedPage - false + CLKOUT4_REQ_FREQ_basicPage + 50.0000 + 4 - LOOP_MAPPING_EN_advancedPage + CLKOUT4_GATE_EN_advancedPage false - CLKOUT2_GATE_EN_advancedPage + CLKIN_SEL_ENABLE_advancedPage false - DYNAMIC_PHASE2_EN_advancedPage + CLKOUT5_EN_advancedPage false - STATIC_DUTY2_basicPage - 120 + CLK_CAS4_EN_advancedPage + false - FBDIV_SEL_advancedPage + CLKOUT5_SEL_advancedPage 0 - CLKOUT1_REQ_DUTY_basicPage - 50.0000 - 4 + STATIC_DUTYF_basicPage + 24 - CLKIN_SEL_EN_ENABLE_advancedPage + STATIC_RATIO3_advancedPage + 16 + + + DYNAMIC_PHASE1_EN_advancedPage false @@ -126,96 +148,100 @@ 16 - CLKIN_SEL_ENABLE_advancedPage + CLKOUT2_REQ_PHASE_basicPage + 0.0000 + 4 + + + CLKOUT4_EN_advancedPage false - CLKIN_FREQ_basicPage - 10.0000 - 4 + CLKOUT3_GATE_EN_advancedPage + false - CLKOUT0_EXT_EN_basicPage + FBMODE_advancedPage false - STATIC_DUTY3_basicPage - 16 + CLKIN_BYPASS_EN_basicPage + false - STATIC_RATIOM_basicPage - 1 + DYNAMIC_RATIO4_EN_advancedPage + false - VCODIV2_ENABLE_advancedPage + CLKSWITCH_FLAG_ENABLE_advancedPage false - DYNAMIC_RATIO2_EN_advancedPage + PLL_PWD_ENABLE_advancedPage false - DYNAMIC_PHASE_EN_advancedPage + MODE false - CLKOUT4_REQ_PHASE_basicPage - 0.0000 - 4 + STATIC_RATIO4_advancedPage + 16 - FEEDBACK_DELAY_ENABLE_basicPage + DYNAMIC_RATIO2_EN_advancedPage false - CLKOUT3_REQ_PHASE_basicPage + CLKOUT1_REQ_PHASE_basicPage 0.0000 4 - CLKOUT4_REQ_FREQ_basicPage - 50.0000 - 4 + CLK_CAS2_EN_basicPage + false - BANDWIDTH_basicPage - LOW + CLKOUT3_EN_advancedPage + false - STATIC_DUTY0_advancedPage + STATIC_PHASE4_advancedPage 16 - STATIC_RATIO2_basicPage - 120 + CLKIN_FREQ_basicPage + 50.0000 + 4 - CLKSWITCH_FLAG_ENABLE_basicPage - false + STATIC_RATIO0_basicPage + 24 - STATIC_RATIO3_basicPage - 16 + CLK_CAS4_EN_basicPage + false - STATIC_DUTY2_advancedPage - 16 + CLKIN_FREQ_advancedPage + 50.0000 + 4 - CLKOUT4_GATE_EN_basicPage + PLL_PWD_ENABLE_basicPage false - PLL_PWD_ENABLE_basicPage + CLKOUT0_GATE_EN_basicPage false - STATIC_DUTY3_advancedPage - 16 + CLKOUT4_EN_basicPage + false - CLKOUT0_EN_advancedPage - true + SHOW_SETTING_EN_basicPage + false CLKOUT2_REQ_FREQ_basicPage @@ -223,350 +249,323 @@ 4 - DYNAMIC_CLKIN_EN_advancedPage + CLKOUT2_GATE_EN_advancedPage false - CLKOUT1_GATE_EN_advancedPage - false + STATIC_RATIO2_basicPage + 120 - CLKOUT0_GATE_EN_advancedPage + DYNAMIC_PHASE2_EN_advancedPage false - STATIC_PHASE1_advancedPage - 16 + CLKOUT1_REQ_FREQ_basicPage + 10.0000 + 4 - CLKOUT2_GATE_EN_basicPage + CLKIN_BYPASS_EN_advancedPage false - DYNAMIC_RATIOF_EN_advancedPage - false + STATIC_RATIOM_basicPage + 1 - STATIC_RATIOI_advancedPage - 2 + CLKOUT1_GATE_EN_basicPage + false - CLKOUT0_EXT_GATE_EN_advancedPage + CLKIN_SEL_ENABLE_basicPage false - STATIC_DUTY1_basicPage - 60 + CLKOUT1_GATE_EN_advancedPage + false - CLKOUT2_EN_basicPage - true + DYNAMIC_PHASE_EN_advancedPage + false - CLKOUT2_REQ_DUTY_basicPage - 50.0000 - 4 + DYNAMIC_LOOP_EN_advancedPage + false - CLKOUT1_GATE_EN_basicPage + CLKOUT3_GATE_EN_basicPage false - FBDIV_SEL_basicPage - 0 + STATIC_DUTY3_basicPage + 16 - STATIC_PHASE0_basicPage - 16 + FEEDBACK_DELAY_VALUE_advancedPage + 0.000 + 3 - FBMODE_advancedPage - false + CLKOUT0_REQ_FREQ_basicPage + 25.0000 + 4 - DYNAMIC_DUTY2_EN_advancedPage + CLKOUT4_GATE_EN_basicPage false - CLKOUT0_REQ_PHASE_basicPage - 0.0000 - 4 + STATIC_RATIO4_basicPage + 16 CLKOUT0_EXT_GATE_EN_basicPage false - RSTODIV_ENABLE_advancedPage + CLKOUT0_EXT_EN_advancedPage false - DYNAMIC_PHASE3_EN_advancedPage - false + CLKOUT2_REQ_DUTY_basicPage + 50.0000 + 4 - DYNAMIC_RATIO4_EN_advancedPage + CLKOUT2_GATE_EN_basicPage false - DYNAMIC_RATIOM_EN_advancedPage + RST_ENABLE_advancedPage false - CLKOUT4_EN_basicPage + CLKOUT2_EN_advancedPage false - STATIC_RATIOM_advancedPage - 1 + FBMODE_basicPage + false - MODE_CFG - 0 + STATIC_DUTY3_advancedPage + 16 - CLK_CAS1_EN_advancedPage - false + STATIC_DUTY2_advancedPage + 16 - STATIC_RATIO4_advancedPage - 16 + STATIC_RATIOI_advancedPage + 2 - CLKOUT0_EN_basicPage - true + FBDIV_SEL_advancedPage + 0 - DYNAMIC_RATIO1_EN_advancedPage + DYNAMIC_PHASE3_EN_advancedPage false - PFDEN_EN_advancedPage + CLKIN_SEL_EN_ENABLE_basicPage false - CLKOUT1_REQ_FREQ_basicPage - 10.0000 + CLKOUT4_REQ_DUTY_basicPage + 50.0000 4 - STATIC_DUTY4_basicPage - 16 + FEEDBACK_DELAY_VALUE_basicPage + 0.000 + 3 - STATIC_DUTY4_advancedPage + STATIC_PHASE1_advancedPage 16 - DEVICE_PGL35 + DYNAMIC_DUTY1_EN_advancedPage false - STATIC_RATIO2_advancedPage - 16 - - - STATIC_PHASE1_basicPage - 16 + CLKSWITCH_FLAG_ENABLE_basicPage + false - CLKIN_FREQ_advancedPage - 50.0000 - 4 + DYNAMIC_RATIOM_EN_advancedPage + false - FB_MODE_advancedPage - 0 + DEVICE_PGL22 + true - CLKOUT2_EN_advancedPage - false + STATIC_PHASE2_basicPage + 16 - CLKOUT4_GATE_EN_advancedPage + FEEDBACK_DELAY_ENABLE_basicPage false - STATIC_PHASE2_basicPage + STATIC_DUTY4_basicPage 16 - CLKOUT5_SEL_advancedPage - 0 - - - CLK_CAS1_EN_basicPage + DYNAMIC_RATIOI_EN_advancedPage false - DYNAMIC_RATIO3_EN_advancedPage + CLK_CAS2_EN_advancedPage false - STATIC_PHASE4_basicPage - 16 + VCODIV2_ENABLE_advancedPage + false - STATIC_RATIO0_advancedPage - 16 + CLKOUT0_EXT_EN_basicPage + false - DYNAMIC_LOOP_EN_advancedPage - false + MODE_CFG + 0 - MODE - false + BANDWIDTH_advancedPage + OPTIMIZED - SHOW_SETTING_EN_basicPage - false + STATIC_RATIO3_basicPage + 16 - CLKOUT3_EN_basicPage - false + STATIC_PHASE0_advancedPage + 16 - PLL_PWD_ENABLE_advancedPage - false + STATIC_PHASE1_basicPage + 16 - CLKOUT3_EN_advancedPage + DYNAMIC_CLKIN_EN_advancedPage false - CLKIN_BYPASS_EN_basicPage + DEVICE_PGL35 false - STATIC_RATIOF_basicPage - 60 + STATIC_RATIO1_advancedPage + 16 - CLK_CAS4_EN_advancedPage + CLKOUT0_EXT_GATE_EN_advancedPage false - FEEDBACK_DELAY_VALUE_advancedPage - 0.000 - 3 - - - CLKOUT4_REQ_DUTY_basicPage + CLKOUT0_REQ_DUTY_basicPage 50.0000 4 - DYNAMIC_PHASE1_EN_advancedPage + DYNAMIC_DUTY2_EN_advancedPage false - STATIC_RATIO4_basicPage + STATIC_DUTY4_advancedPage 16 - CLK_CAS3_EN_basicPage - false - - - STATIC_DUTY0_basicPage - 24 + STATIC_RATIO0_advancedPage + 16 - CLKOUT2_REQ_PHASE_basicPage - 0.0000 - 4 + FB_MODE_advancedPage + 0 - STATIC_PHASE2_advancedPage + STATIC_RATIOF_advancedPage 16 - CLKOUT4_EN_advancedPage - false + STATIC_RATIOI_basicPage + 2 - CLKIN_BYPASS_EN_advancedPage + DYNAMIC_PHASE4_EN_advancedPage false - STATIC_DUTYF_basicPage - 60 + CLKOUT3_REQ_DUTY_basicPage + 50.0000 + 4 - CLKOUT3_GATE_EN_advancedPage + DYNAMIC_RATIO1_EN_advancedPage false - FEEDBACK_DELAY_VALUE_basicPage - 0.000 - 3 + STATIC_DUTY2_basicPage + 120 - CLK_CAS2_EN_advancedPage - false + STATIC_PHASE3_advancedPage + 16 - STATIC_PHASE3_basicPage + STATIC_PHASE2_advancedPage 16 - STATIC_RATIO1_basicPage - 60 + DYNAMIC_RATIO3_EN_advancedPage + false - CLKOUT3_GATE_EN_basicPage + DYNAMIC_DUTY3_EN_advancedPage false - CLKOUT3_REQ_DUTY_basicPage - 50.0000 - 4 + BANDWIDTH_basicPage + OPTIMIZED - CLKOUT1_REQ_PHASE_basicPage - 0.0000 - 4 + STATIC_PHASE0_basicPage + 16 - CLKOUT0_REQ_FREQ_basicPage - 25.0000 - 4 + STATIC_RATIO1_basicPage + 60 - DYNAMIC_DUTY3_EN_advancedPage + DYNAMIC_RATIOF_EN_advancedPage false - BANDWIDTH_advancedPage - OPTIMIZED - - - DYNAMIC_RATIO0_EN_advancedPage + CLKOUT5_GATE_EN_advancedPage false - STATIC_RATIO3_advancedPage - 16 + FB_MODE_basicPage + 0 - CLK_CAS4_EN_basicPage + CLK_CAS1_EN_advancedPage false - STATIC_PHASE3_advancedPage - 16 - - - CLKOUT5_GATE_EN_advancedPage - false + CLKOUT0_EN_advancedPage + true - CLKIN_SEL_ENABLE_basicPage + CLKOUT1_EN_advancedPage false - DYNAMIC_RATIOI_EN_advancedPage + CLK_CAS1_EN_basicPage false @@ -574,44 +573,45 @@ true - DYNAMIC_PHASE0_EN_advancedPage + DYNAMIC_DUTY4_EN_advancedPage false - DEVICE_PGL12 - false + CLKOUT3_REQ_PHASE_basicPage + 0.0000 + 4 - CLKOUT0_GATE_EN_basicPage + DYNAMIC_DUTY0_EN_advancedPage false - DYNAMIC_DUTY0_EN_advancedPage + CLKOUT0_GATE_EN_advancedPage false - CLK_CAS2_EN_basicPage + DEVICE_PGL12 false - STATIC_RATIOI_basicPage - 1 + CLK_CAS3_EN_basicPage + false - DYNAMIC_DUTY4_EN_advancedPage + CLK_CAS3_EN_advancedPage false - CLKIN_SEL_EN_ENABLE_basicPage + CLKIN_SEL_EN_ENABLE_advancedPage false - STATIC_RATIOF_advancedPage + STATIC_PHASE4_basicPage 16 - STATIC_RATIO1_advancedPage - 16 + STATIC_DUTY1_basicPage + 60 diff --git a/ipcore/SPLL/SPLL.v b/ipcore/SPLL/SPLL.v index 43448c9..c71a4d2 100644 --- a/ipcore/SPLL/SPLL.v +++ b/ipcore/SPLL/SPLL.v @@ -26,20 +26,20 @@ module SPLL ( pll_lock ); - localparam real CLKIN_FREQ = 10.0; - localparam integer STATIC_RATIOI = 1; + localparam real CLKIN_FREQ = 50.0; + localparam integer STATIC_RATIOI = 2; localparam integer STATIC_RATIO0 = 24; localparam integer STATIC_RATIO1 = 60; localparam integer STATIC_RATIO2 = 120; localparam integer STATIC_RATIO3 = 16; localparam integer STATIC_RATIO4 = 16; - localparam integer STATIC_RATIOF = 60; + localparam integer STATIC_RATIOF = 24; localparam integer STATIC_DUTY0 = 24; localparam integer STATIC_DUTY1 = 60; localparam integer STATIC_DUTY2 = 120; localparam integer STATIC_DUTY3 = 16; localparam integer STATIC_DUTY4 = 16; - localparam integer STATIC_DUTYF = 60; + localparam integer STATIC_DUTYF = 24; localparam integer STATIC_PHASE0 = 16; localparam integer STATIC_PHASE1 = 16; localparam integer STATIC_PHASE2 = 16; @@ -58,7 +58,7 @@ module SPLL ( localparam CLKOUT4_GATE_EN = "FALSE"; localparam FBMODE = "FALSE"; localparam integer FBDIV_SEL = 0; - localparam BANDWIDTH = "LOW"; + localparam BANDWIDTH = "OPTIMIZED"; localparam PFDEN_EN = "FALSE"; localparam VCOCLK_DIV2 = 1'b0; localparam DYNAMIC_RATIOI_EN = "FALSE"; diff --git a/ipcore/SPLL/SPLL_tb.v b/ipcore/SPLL/SPLL_tb.v index d6ae836..60dd5fe 100644 --- a/ipcore/SPLL/SPLL_tb.v +++ b/ipcore/SPLL/SPLL_tb.v @@ -20,7 +20,7 @@ module SPLL_tb (); -localparam CLKIN_FREQ = 10.0; +localparam CLKIN_FREQ = 50.0; localparam integer FBDIV_SEL = 0; localparam FBMODE = "FALSE"; diff --git a/ipcore/SPLL/generate.log b/ipcore/SPLL/generate.log index 48d2ac2..a14cc59 100644 --- a/ipcore/SPLL/generate.log +++ b/ipcore/SPLL/generate.log @@ -1,6 +1,6 @@ IP Generator (Version 2021.1-SP7 build 86875) Check out license ... -Start generating at 2024-01-10 21:58 +Start generating at 2024-01-11 09:39 Instance: SPLL (D:\workspace\fpga_demo\led_test\ipcore\SPLL\SPLL.idf) IP: PLL (1.5) Part: Logos-PGL22G-MBG324--6 diff --git a/led_test.pds b/led_test.pds index 4193bc4..666d603 100644 --- a/led_test.pds +++ b/led_test.pds @@ -1,5 +1,5 @@ (_flow fab_demo "2021.1-SP7" - (_comment "Generated by Fabric Compiler (version on 2021.1-SP7) at Thu Jan 11 09:23:14 2024") + (_comment "Generated by Fabric Compiler (version on 2021.1-SP7) at Thu Jan 11 11:12:15 2024") (_version "1.0.5") (_status "initial") (_project @@ -19,11 +19,11 @@ (_input (_file "source/src/top.v" + "Top:" (_format verilog) - (_timespec "2024-01-11T09:22:07") + (_timespec "2024-01-11T11:12:05") ) (_file "source/src/spi_reg_reader.v" (_format verilog) - (_timespec "2024-01-08T22:12:49") + (_timespec "2024-01-11T09:43:30") ) (_file "source/src/zutils/zutils_pluse_generator.v" (_format verilog) @@ -67,7 +67,7 @@ ) (_file "source/src/rd_data_router.v" (_format verilog) - (_timespec "2024-01-08T22:15:00") + (_timespec "2024-01-11T10:28:39") ) (_file "source/src/zutils/zutils_reset_sig_gen.v" (_format verilog) @@ -87,7 +87,7 @@ ) (_file "source/src/xsync_internal_generator.v" (_format verilog) - (_timespec "2024-01-11T09:21:24") + (_timespec "2024-01-11T11:11:25") ) (_file "source/src/zutils/zutils_pwm_generator_advanced.v" (_format verilog) @@ -138,9 +138,9 @@ (_widget wgt_my_ips_src (_input (_ip "ipcore/SPLL/SPLL.idf" - (_timespec "2024-01-10T21:58:34") + (_timespec "2024-01-11T09:39:18") (_ip_source_item "ipcore/SPLL/SPLL.v" - (_timespec "2024-01-10T21:58:33") + (_timespec "2024-01-11T09:39:18") ) ) (_ip "ipcore/genlock_sig_gen_pll/genlock_sig_gen_pll.idf" @@ -195,21 +195,21 @@ ) (_task tsk_compile (_command cmd_compile - (_gci_state (_integer 2)) + (_gci_state (_integer 3)) (_db_output (_file "compile/Top_comp.adf" (_format adif) - (_timespec "2024-01-11T09:22:17") + (_timespec "2024-01-11T11:11:40") ) ) (_output (_file "compile/Top.cmr" (_format verilog) - (_timespec "2024-01-11T09:22:16") + (_timespec "2024-01-11T11:11:39") ) (_file "compile/cmr.db" (_format text) - (_timespec "2024-01-11T09:22:17") + (_timespec "2024-01-11T11:11:40") ) ) ) @@ -225,21 +225,21 @@ (_db_output (_file "synthesize/Top_syn.adf" (_format adif) - (_timespec "2024-01-11T09:22:26") + (_timespec "2024-01-11T11:12:09") ) ) (_output (_file "synthesize/Top_syn.vm" (_format structural_verilog) - (_timespec "2024-01-11T09:22:27") + (_timespec "2024-01-11T11:12:12") ) (_file "synthesize/Top.snr" (_format text) - (_timespec "2024-01-11T09:22:27") + (_timespec "2024-01-11T11:12:14") ) (_file "synthesize/snr.db" (_format text) - (_timespec "2024-01-11T09:22:27") + (_timespec "2024-01-11T11:12:15") ) ) ) @@ -256,34 +256,14 @@ ) (_task tsk_devmap (_command cmd_devmap - (_gci_state (_integer 2)) - (_db_output - (_file "device_map/Top_map.adf" - (_format adif) - (_timespec "2024-01-11T09:22:30") - ) - ) - (_output - (_file "device_map/Top_dmr.prt" - (_format text) - (_timespec "2024-01-11T09:22:30") - ) - (_file "device_map/Top.dmr" - (_format text) - (_timespec "2024-01-11T09:22:30") - ) - (_file "device_map/dmr.db" - (_format text) - (_timespec "2024-01-11T09:22:30") - ) - ) + (_gci_state (_integer 0)) ) (_widget wgt_edit_placement_cons (_attribute _click_to_run (_switch ON)) (_input (_file "device_map/led_test.pcf" (_format pcf) - (_timespec "2024-01-11T09:22:30") + (_timespec "2024-01-11T09:43:56") ) ) ) @@ -293,39 +273,7 @@ ) (_task tsk_pnr (_command cmd_pnr - (_gci_state (_integer 2)) - (_db_output - (_file "place_route/Top_pnr.adf" - (_format adif) - (_timespec "2024-01-11T09:23:00") - ) - ) - (_output - (_file "place_route/Top.prr" - (_format text) - (_timespec "2024-01-11T09:23:00") - ) - (_file "place_route/Top_prr.prt" - (_format text) - (_timespec "2024-01-11T09:23:00") - ) - (_file "place_route/clock_utilization.txt" - (_format text) - (_timespec "2024-01-11T09:23:00") - ) - (_file "place_route/Top_plc.adf" - (_format adif) - (_timespec "2024-01-11T09:22:49") - ) - (_file "place_route/Top_pnr.netlist" - (_format text) - (_timespec "2024-01-11T09:23:00") - ) - (_file "place_route/prr.db" - (_format text) - (_timespec "2024-01-11T09:23:00") - ) - ) + (_gci_state (_integer 0)) ) (_widget wgt_power_calculator (_attribute _click_to_run (_switch ON)) @@ -334,24 +282,8 @@ (_attribute _click_to_run (_switch ON)) ) (_command cmd_report_post_pnr_timing - (_gci_state (_integer 2)) + (_gci_state (_integer 0)) (_attribute _auto_exe_lock (_switch OFF)) - (_db_output - (_file "report_timing/Top_rtp.adf" - (_format adif) - (_timespec "2024-01-11T09:23:05") - ) - ) - (_output - (_file "report_timing/Top.rtr" - (_format text) - (_timespec "2024-01-11T09:23:05") - ) - (_file "report_timing/rtr.db" - (_format text) - (_timespec "2024-01-11T09:23:05") - ) - ) ) (_widget wgt_arch_browser (_attribute _click_to_run (_switch ON)) @@ -369,25 +301,7 @@ ) (_task tsk_gen_bitstream (_command cmd_gen_bitstream - (_gci_state (_integer 2)) - (_output - (_file "generate_bitstream/Top.sbit" - (_format text) - (_timespec "2024-01-11T09:23:14") - ) - (_file "generate_bitstream/Top.smsk" - (_format text) - (_timespec "2024-01-11T09:23:14") - ) - (_file "generate_bitstream/Top.bgr" - (_format text) - (_timespec "2024-01-11T09:23:14") - ) - (_file "generate_bitstream/bgr.db" - (_format text) - (_timespec "2024-01-11T09:23:14") - ) - ) + (_gci_state (_integer 0)) ) ) ) diff --git a/source/src/config.v b/source/src/config.v deleted file mode 100644 index 9966975..0000000 --- a/source/src/config.v +++ /dev/null @@ -1,22 +0,0 @@ -//STM32寄存器地址 -`define REG_ADD_OFF_STM32 16'h0000 -`define REG_ADD_OFF_FPGA_TEST 16'h00020 -//控制中心寄存器地址 -`define REG_ADD_OFF_CONTROL_SENSOR 16'h00030 -//输入组件 -`define REG_ADD_OFF_TTLIN1 16'h0100 -`define REG_ADD_OFF_TTLIN2 16'h0110 -`define REG_ADD_OFF_TTLIN3 16'h0120 -`define REG_ADD_OFF_TTLIN4 16'h0130 -`define REG_ADD_OFF_TIMECODE_IN 16'h0140 -`define REG_ADD_OFF_GENLOCK_IN 16'h0150 -//输出组件 -`define REG_ADD_OFF_TTLOUT1 16'h0200 -`define REG_ADD_OFF_TTLOUT2 16'h0210 -`define REG_ADD_OFF_TTLOUT3 16'h0220 -`define REG_ADD_OFF_TTLOUT4 16'h0230 -`define REG_ADD_OFF_TIMECODE_OUT 16'h0240 -`define REG_ADD_OFF_GENLOCK_OUT 16'h0250 -`define REG_ADD_OFF_STM32_IF 16'h0260 -//调试组件 -`define REG_ADD_OFF_DEBUGER 16'h0300 diff --git a/source/src/debuger.v b/source/src/debuger.v index a781cca..a7b2587 100644 --- a/source/src/debuger.v +++ b/source/src/debuger.v @@ -7,7 +7,7 @@ module rd_data_router ( input [31:0] stm32_rd_data, input [31:0] fpga_test_rd_data, - input [31:0] control_sensor_rd_data, + input [31:0] xsync_internal_sig_generator_rd_data, input [31:0] ttlin1_rd_data, input [31:0] ttlin2_rd_data, input [31:0] ttlin3_rd_data, diff --git a/source/src/rd_data_router.v b/source/src/rd_data_router.v index 444dcae..c0e369c 100644 --- a/source/src/rd_data_router.v +++ b/source/src/rd_data_router.v @@ -1,14 +1,32 @@ -`include "config.v" /* * Hacky baud rate generator to divide a 50MHz clock into a 115200 baud * rx/tx pair where the rx clcken oversamples by 16x. */ -module rd_data_router ( +module rd_data_router #( + parameter REG_ADD_OFF_STM32 = 0, + parameter REG_ADD_OFF_FPGA_TEST = 0, + parameter REG_ADD_OFF_XSYNC_INTERNAL_SIG_GENERATOR = 0, + parameter REG_ADD_OFF_TTLIN1 = 0, + parameter REG_ADD_OFF_TTLIN2 = 0, + parameter REG_ADD_OFF_TTLIN3 = 0, + parameter REG_ADD_OFF_TTLIN4 = 0, + parameter REG_ADD_OFF_TIMECODE_IN = 0, + parameter REG_ADD_OFF_GENLOCK_IN = 0, + parameter REG_ADD_OFF_TTLOUT1 = 0, + parameter REG_ADD_OFF_TTLOUT2 = 0, + parameter REG_ADD_OFF_TTLOUT3 = 0, + parameter REG_ADD_OFF_TTLOUT4 = 0, + parameter REG_ADD_OFF_TIMECODE_OUT = 0, + parameter REG_ADD_OFF_GENLOCK_OUT = 0, + parameter REG_ADD_OFF_STM32_IF = 0, + parameter REG_ADD_OFF_DEBUGER = 0 + +) ( input [31:0] addr, input [31:0] stm32_rd_data, input [31:0] fpga_test_rd_data, - input [31:0] control_sensor_rd_data, + input [31:0] xsync_internal_sig_generator_rd_data, input [31:0] ttlin1_rd_data, input [31:0] ttlin2_rd_data, input [31:0] ttlin3_rd_data, @@ -34,23 +52,23 @@ module rd_data_router ( always @(*) begin case (addr_group) - (`REG_ADD_OFF_STM32): rd_data_out = stm32_rd_data; - (`REG_ADD_OFF_FPGA_TEST): rd_data_out = fpga_test_rd_data; - (`REG_ADD_OFF_CONTROL_SENSOR): rd_data_out = control_sensor_rd_data; - (`REG_ADD_OFF_TTLIN1): rd_data_out = ttlin1_rd_data; - (`REG_ADD_OFF_TTLIN2): rd_data_out = ttlin2_rd_data; - (`REG_ADD_OFF_TTLIN3): rd_data_out = ttlin3_rd_data; - (`REG_ADD_OFF_TTLIN4): rd_data_out = ttlin4_rd_data; - (`REG_ADD_OFF_TIMECODE_IN): rd_data_out = timecode_in_rd_data; - (`REG_ADD_OFF_GENLOCK_IN): rd_data_out = genlock_in_rd_data; - (`REG_ADD_OFF_TTLOUT1): rd_data_out = ttlout1_rd_data; - (`REG_ADD_OFF_TTLOUT2): rd_data_out = ttlout2_rd_data; - (`REG_ADD_OFF_TTLOUT3): rd_data_out = ttlout3_rd_data; - (`REG_ADD_OFF_TTLOUT4): rd_data_out = ttlout4_rd_data; - (`REG_ADD_OFF_TIMECODE_OUT): rd_data_out = timecode_out_rd_data; - (`REG_ADD_OFF_GENLOCK_OUT): rd_data_out = genlock_out_rd_data; - (`REG_ADD_OFF_STM32_IF): rd_data_out = stm32_if_rd_data; - (`REG_ADD_OFF_DEBUGER): rd_data_out = debuger_rd_data; + REG_ADD_OFF_STM32: rd_data_out = stm32_rd_data; + REG_ADD_OFF_FPGA_TEST: rd_data_out = fpga_test_rd_data; + REG_ADD_OFF_XSYNC_INTERNAL_SIG_GENERATOR: rd_data_out = xsync_internal_sig_generator_rd_data; + REG_ADD_OFF_TTLIN1: rd_data_out = ttlin1_rd_data; + REG_ADD_OFF_TTLIN2: rd_data_out = ttlin2_rd_data; + REG_ADD_OFF_TTLIN3: rd_data_out = ttlin3_rd_data; + REG_ADD_OFF_TTLIN4: rd_data_out = ttlin4_rd_data; + REG_ADD_OFF_TIMECODE_IN: rd_data_out = timecode_in_rd_data; + REG_ADD_OFF_GENLOCK_IN: rd_data_out = genlock_in_rd_data; + REG_ADD_OFF_TTLOUT1: rd_data_out = ttlout1_rd_data; + REG_ADD_OFF_TTLOUT2: rd_data_out = ttlout2_rd_data; + REG_ADD_OFF_TTLOUT3: rd_data_out = ttlout3_rd_data; + REG_ADD_OFF_TTLOUT4: rd_data_out = ttlout4_rd_data; + REG_ADD_OFF_TIMECODE_OUT: rd_data_out = timecode_out_rd_data; + REG_ADD_OFF_GENLOCK_OUT: rd_data_out = genlock_out_rd_data; + REG_ADD_OFF_STM32_IF: rd_data_out = stm32_if_rd_data; + REG_ADD_OFF_DEBUGER: rd_data_out = debuger_rd_data; default: rd_data_out = 0; endcase end diff --git a/source/src/spi_reg_reader.v b/source/src/spi_reg_reader.v index 23eedc5..b663241 100644 --- a/source/src/spi_reg_reader.v +++ b/source/src/spi_reg_reader.v @@ -31,7 +31,7 @@ module spi_reg_reader ( zutils_signal_filter #( - .FILTER_COUNT(5) + .FILTER_COUNT(2) ) cs_filter ( .clk(clk), .rst_n(rst_n), @@ -40,7 +40,7 @@ module spi_reg_reader ( ); zutils_signal_filter #( - .FILTER_COUNT(2) + .FILTER_COUNT(1) ) clk_filter ( .clk(clk), .rst_n(rst_n), @@ -49,7 +49,7 @@ module spi_reg_reader ( ); zutils_signal_filter #( - .FILTER_COUNT(2) + .FILTER_COUNT(1) ) spi_rx_filter ( .clk(clk), .rst_n(rst_n), diff --git a/source/src/top.v b/source/src/top.v index 137b18b..1765532 100644 --- a/source/src/top.v +++ b/source/src/top.v @@ -1,4 +1,3 @@ -`include "config.v" `timescale 1ns / 1ns module Top ( input ex_clk, @@ -106,9 +105,28 @@ module Top ( ); localparam HARDWARE_TEST_MODE = 1; - - - + //STM32寄存器地址 + localparam REG_ADD_OFF_STM32 = 16'h0000; + localparam REG_ADD_OFF_FPGA_TEST = 16'h00020; + //控制中心寄存器地址 + localparam REG_ADD_OFF_XSYNC_INTERNAL_SIG_GENERATOR = 16'h00030; + //输入组件 + localparam REG_ADD_OFF_TTLIN1 = 16'h0100; + localparam REG_ADD_OFF_TTLIN2 = 16'h0110; + localparam REG_ADD_OFF_TTLIN3 = 16'h0120; + localparam REG_ADD_OFF_TTLIN4 = 16'h0130; + localparam REG_ADD_OFF_TIMECODE_IN = 16'h0140; + localparam REG_ADD_OFF_GENLOCK_IN = 16'h0150; + //输出组件 + localparam REG_ADD_OFF_TTLOUT1 = 16'h0200; + localparam REG_ADD_OFF_TTLOUT2 = 16'h0210; + localparam REG_ADD_OFF_TTLOUT3 = 16'h0220; + localparam REG_ADD_OFF_TTLOUT4 = 16'h0230; + localparam REG_ADD_OFF_TIMECODE_OUT = 16'h0240; + localparam REG_ADD_OFF_GENLOCK_OUT = 16'h0250; + localparam REG_ADD_OFF_STM32_IF = 16'h0260; + //调试组件 + localparam REG_ADD_OFF_DEBUGER = 16'h0300; SPLL spll ( .clkin1(ex_clk), // input @@ -162,9 +180,9 @@ module Top ( .spi_tx_pin(spi2_tx_pin) ); - wire [31:0] stm32_rd_data; - wire [31:0] fpga_test_rd_data; - wire [31:0] control_sensor_rd_data; + wire [31:0] stm32_rd_data; // + wire [31:0] fpga_test_rd_data; // + wire [31:0] xsync_internal_sig_generator_rd_data; wire [31:0] ttlin1_rd_data; wire [31:0] ttlin2_rd_data; wire [31:0] ttlin3_rd_data; @@ -185,7 +203,7 @@ module Top ( * TEST_SPI_REG * *******************************************************************************/ zutils_register16 #( - .REG_START_ADD(`REG_ADD_OFF_FPGA_TEST), + .REG_START_ADD(REG_ADD_OFF_FPGA_TEST), .REG0_INIT(31'h0000_0000_0000_0001), .REG1_INIT(31'h0000_0000_0000_0010), .REG2_INIT(31'h0000_0000_0000_0100), @@ -214,69 +232,123 @@ module Top ( /******************************************************************************* * 信号源 * *******************************************************************************/ - // level0 = 0, // 0 - // level1 = 1, // 1 - wire ttlin1_module_raw_sig; // ttl1输入模块原始信号 2 - wire ttlin1_module_sig_divide; // ttl1输入模块分频信号 3 - wire ttlin2_module_raw_sig; // ttl2输入模块原始信号 4 - wire ttlin2_module_sig_divide; // ttl2输入模块分频信号 5 - wire ttlin3_module_raw_sig; // ttl3输入模块原始信号 6 - wire ttlin3_module_sig_divide; // ttl3输入模块分频信号 7 - wire ttlin4_module_raw_sig; // ttl4输入模块原始信号 8 - wire ttlin4_module_sig_divide; // ttl4输入模块分频信号 9 - wire genlockin_module_freq_sig; // genlock输入模块频率信号 10 - wire timecodein_module_trigger_sig; // timecode输入模块触发信号 11 - wire internal_camera_sync_sig; // 内部相机同步信号 12 - wire internal_timecode_trigger_sig; // 内部timecode触发信号 13 - wire internal_genlock_freq_sig; // 内部genlock频率信号 14 - wire internal_work_state_sig; // 内部工作状态信号 15 - wire internal_100hz_output; // 内部工作状态信号 16 - - xsync_internal_generator xsync_internal_generator_ins ( - .clk (sys_clk), - .rst_n(sys_rst_n) - ); + wire ISIG_logic0; // 逻辑0 + wire ISIG_logic1; // 逻辑1 + wire ISIG_ttlin1_module_ext; // ttl1输入模块原始信号 + wire ISIG_ttlin1_module_divide; // ttl1输入模块分频信号 + wire ISIG_ttlin2_module_ext; // ttl2输入模块原始信号 + wire ISIG_ttlin2_module_divide; // ttl2输入模块分频信号 + wire ISIG_ttlin3_module_ext; // ttl3输入模块原始信号 + wire ISIG_ttlin3_module_divide; // ttl3输入模块分频信号 + wire ISIG_ttlin4_module_ext; // ttl4输入模块原始信号 + wire ISIG_ttlin4_module_divide; // ttl4输入模块分频信号 + wire ISIG_internal_en_flag; // 内部使能状态信号输出 + wire ISIG_genlock_frame_sync_ext; // 外部genlock帧同步信号 + wire ISIG_genlock_frame_sync_internal; // 内部genlock帧同步信号 + wire ISIG_timecode_frame_sync_ext; // 外部timecode帧同步信号 + wire ISIG_timecode_frame_sync_internal; // 内部timecode帧同步信号 + wire ISIG_timecode_serial_data_ext; // 外部timecode串行数据输入 + wire ISIG_timecode_serial_data_internal; // 内部timecode串行数据输入 + wire ISIG_internal_100hz; // 100hz测试信号 + + wire [63:0] ISIGBUS64_timecode_data_ext; + wire [63:0] ISIGBUS64_timecode_data_internal; + + assign ISIG_genlock_frame_sync_ext = genlock_in_vsync; + assign ISIG_logic0 = 0; + assign ISIG_logic1 = 1; + + /******************************************************************************* + * TTL输出模块信号源分配 * + *******************************************************************************/ wire [31:0] ttl_output_module_source_sig_af; + assign ttl_output_module_source_sig_af[0] = ISIG_logic0; + assign ttl_output_module_source_sig_af[1] = ISIG_logic1; + assign ttl_output_module_source_sig_af[2] = ISIG_ttlin1_module_ext; + assign ttl_output_module_source_sig_af[3] = ISIG_ttlin1_module_divide; + assign ttl_output_module_source_sig_af[4] = ISIG_ttlin2_module_ext; + assign ttl_output_module_source_sig_af[5] = ISIG_ttlin2_module_divide; + assign ttl_output_module_source_sig_af[6] = ISIG_ttlin3_module_ext; + assign ttl_output_module_source_sig_af[7] = ISIG_ttlin3_module_divide; + assign ttl_output_module_source_sig_af[8] = ISIG_ttlin4_module_ext; + assign ttl_output_module_source_sig_af[9] = ISIG_ttlin4_module_divide; + assign ttl_output_module_source_sig_af[10] = ISIG_internal_en_flag; + assign ttl_output_module_source_sig_af[11] = ISIG_genlock_frame_sync_ext; + assign ttl_output_module_source_sig_af[12] = ISIG_genlock_frame_sync_internal; + assign ttl_output_module_source_sig_af[13] = ISIG_timecode_frame_sync_ext; + assign ttl_output_module_source_sig_af[14] = ISIG_timecode_frame_sync_internal; + assign ttl_output_module_source_sig_af[15] = ISIG_timecode_serial_data_ext; + assign ttl_output_module_source_sig_af[16] = ISIG_timecode_serial_data_internal; + assign ttl_output_module_source_sig_af[31] = ISIG_internal_100hz; + + + wire ISIG_logic0; // 逻辑0 + wire ISIG_logic1; // 逻辑1 + wire ISIG_ttlin1_module_ext; // ttl1输入模块原始信号 + wire ISIG_ttlin1_module_divide; // ttl1输入模块分频信号 + wire ISIG_ttlin2_module_ext; // ttl2输入模块原始信号 + wire ISIG_ttlin2_module_divide; // ttl2输入模块分频信号 + wire ISIG_ttlin3_module_ext; // ttl3输入模块原始信号 + wire ISIG_ttlin3_module_divide; // ttl3输入模块分频信号 + wire ISIG_ttlin4_module_ext; // ttl4输入模块原始信号 + wire ISIG_ttlin4_module_divide; // ttl4输入模块分频信号 + wire ISIG_en_flag_internal; // 内部使能状态信号输出 + wire ISIG_genlock_frame_sync_ext; // 外部genlock帧同步信号 + wire ISIG_genlock_frame_sync_internal; // 内部genlock帧同步信号 + wire ISIG_timecode_frame_sync_ext; // 外部timecode帧同步信号 + wire ISIG_timecode_frame_sync_internal; // 内部timecode帧同步信号 + wire ISIG_timecode_serial_data_ext; // 外部timecode串行数据输入 + wire ISIG_timecode_serial_data_internal; // 内部timecode串行数据输入 + wire ISIG_internal_100hz; // 100hz测试信号 + + + + xsync_internal_generator #( + .REG_START_ADD (REG_ADD_OFF_XSYNC_INTERNAL_SIG_GENERATOR), + .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ) + ) xsync_internal_generator_ins ( + .clk(sys_clk), + .rst_n(sys_rst_n), + .addr(reg_reader_bus_addr), + .wr_data(reg_reader_bus_wr_data), + .wr_en(reg_reader_bus_wr_en), + .rd_data(xsync_internal_sig_generator_rd_data), + + .ext_ttlin1_module_raw_sig(ISIG_ttlin1_module_ext), + .ext_ttlin2_module_raw_sig(ISIG_ttlin2_module_ext), + .ext_ttlin3_module_raw_sig(ISIG_ttlin3_module_ext), + .ext_ttlin4_module_raw_sig(ISIG_ttlin4_module_ext), + .ext_timecode_tigger_sig(ISIG_timecode_frame_sync_ext), + .ext_timecode_data(ISIGBUS64_timecode_data_ext), + .ext_genlock_signal(ISIG_genlock_frame_sync_ext), + + .out_timecode_tirgger_sig(ISIG_timecode_frame_sync_internal), //输出时码译码有效信号 + .out_timecode_sig(ISIGBUS64_timecode_data_internal), //[63:0] 输出时间 + .out_timecode_serial_sig(ISIG_timecode_serial_data_internal), //TIMECODE串行数据输出 + .out_genlock_sig(ISIG_genlock_frame_sync_internal), + .out_en_flag(ISIG_en_flag_internal) + ); + + /******************************************************************************* + * ISIG_internal_100hz信号生成 * + *******************************************************************************/ zutils_pwm_generator #( .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ), .OUTPUT_FREQ(100) ) pwm100hz_gen ( .clk(sys_clk), .rst_n(sys_rst_n), - .output_signal(internal_100hz_output) + .output_signal(ISIG_internal_100hz) ); - /******************************************************************************* * 输出组件 * *******************************************************************************/ - - - - assign ttl_output_module_source_sig_af[0] = 0; - assign ttl_output_module_source_sig_af[1] = 1; - assign ttl_output_module_source_sig_af[2] = ttlin1_module_raw_sig; - assign ttl_output_module_source_sig_af[3] = ttlin1_module_sig_divide; - assign ttl_output_module_source_sig_af[4] = ttlin2_module_raw_sig; - assign ttl_output_module_source_sig_af[5] = ttlin2_module_sig_divide; - assign ttl_output_module_source_sig_af[6] = ttlin3_module_raw_sig; - assign ttl_output_module_source_sig_af[7] = ttlin3_module_sig_divide; - assign ttl_output_module_source_sig_af[8] = ttlin4_module_raw_sig; - assign ttl_output_module_source_sig_af[9] = ttlin4_module_sig_divide; - assign ttl_output_module_source_sig_af[10] = genlockin_module_freq_sig; - assign ttl_output_module_source_sig_af[11] = timecodein_module_trigger_sig; - assign ttl_output_module_source_sig_af[12] = internal_camera_sync_sig; - assign ttl_output_module_source_sig_af[13] = internal_timecode_trigger_sig; - assign ttl_output_module_source_sig_af[14] = internal_genlock_freq_sig; - assign ttl_output_module_source_sig_af[15] = internal_work_state_sig; - assign ttl_output_module_source_sig_af[16] = internal_100hz_output; - - ttl_output #( - .REG_START_ADD(`REG_ADD_OFF_TTLOUT1), + .REG_START_ADD(REG_ADD_OFF_TTLOUT1), .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ), .ID(1) ) ttl_output_1 ( @@ -295,7 +367,7 @@ module Top ( ); ttl_output #( - .REG_START_ADD(`REG_ADD_OFF_TTLOUT2), + .REG_START_ADD(REG_ADD_OFF_TTLOUT2), .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ), .ID(2) ) ttl_output_2 ( @@ -314,7 +386,7 @@ module Top ( ); ttl_output #( - .REG_START_ADD(`REG_ADD_OFF_TTLOUT3), + .REG_START_ADD(REG_ADD_OFF_TTLOUT3), .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ), .ID(3) ) ttl_output_3 ( @@ -333,7 +405,7 @@ module Top ( ); ttl_output #( - .REG_START_ADD(`REG_ADD_OFF_TTLOUT4), + .REG_START_ADD(REG_ADD_OFF_TTLOUT4), .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ), .ID(4) ) ttl_output_4 ( @@ -352,12 +424,30 @@ module Top ( ); - rd_data_router rd_data_router_inst ( + rd_data_router #( + .REG_ADD_OFF_STM32(REG_ADD_OFF_STM32), + .REG_ADD_OFF_FPGA_TEST(REG_ADD_OFF_FPGA_TEST), + .REG_ADD_OFF_XSYNC_INTERNAL_SIG_GENERATOR(REG_ADD_OFF_XSYNC_INTERNAL_SIG_GENERATOR), + .REG_ADD_OFF_TTLIN1(REG_ADD_OFF_TTLIN1), + .REG_ADD_OFF_TTLIN2(REG_ADD_OFF_TTLIN2), + .REG_ADD_OFF_TTLIN3(REG_ADD_OFF_TTLIN3), + .REG_ADD_OFF_TTLIN4(REG_ADD_OFF_TTLIN4), + .REG_ADD_OFF_TIMECODE_IN(REG_ADD_OFF_TIMECODE_IN), + .REG_ADD_OFF_GENLOCK_IN(REG_ADD_OFF_GENLOCK_IN), + .REG_ADD_OFF_TTLOUT1(REG_ADD_OFF_TTLOUT1), + .REG_ADD_OFF_TTLOUT2(REG_ADD_OFF_TTLOUT2), + .REG_ADD_OFF_TTLOUT3(REG_ADD_OFF_TTLOUT3), + .REG_ADD_OFF_TTLOUT4(REG_ADD_OFF_TTLOUT4), + .REG_ADD_OFF_TIMECODE_OUT(REG_ADD_OFF_TIMECODE_OUT), + .REG_ADD_OFF_GENLOCK_OUT(REG_ADD_OFF_GENLOCK_OUT), + .REG_ADD_OFF_STM32_IF(REG_ADD_OFF_STM32_IF), + .REG_ADD_OFF_DEBUGER(REG_ADD_OFF_DEBUGER) + ) rd_data_router_inst ( .addr(reg_reader_bus_addr), .stm32_rd_data(stm32_rd_data), .fpga_test_rd_data(fpga_test_rd_data), - .control_sensor_rd_data(control_sensor_rd_data), + .xsync_internal_sig_generator_rd_data(xsync_internal_sig_generator_rd_data), .ttlin1_rd_data(ttlin1_rd_data), .ttlin2_rd_data(ttlin2_rd_data), .ttlin3_rd_data(ttlin3_rd_data), diff --git a/source/src/xsync_internal_generator.v b/source/src/xsync_internal_generator.v index 02231a2..48bd597 100644 --- a/source/src/xsync_internal_generator.v +++ b/source/src/xsync_internal_generator.v @@ -39,8 +39,7 @@ module xsync_internal_generator #( parameter REG_START_ADD = 0, parameter SYS_CLOCK_FREQ = 10000000, - parameter TEST = 0, - parameter ID = 1 + parameter TEST = 0 ) ( input clk, //clock input input rst_n, //asynchronous reset input, low active