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update uart_reg_reader

master
zhaohe 2 years ago
parent
784e5a0902
commit
edc2742d06
3 changed files with 78 additions and 68 deletions
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  1. 70
      led_test.pds
  2. 66
      source/src/uart_reg_reader.v
  3. 4
      source/test/test_uart_reg_reader.v

70
led_test.pds
View File

@ -1,5 +1,5 @@
(_flow fab_demo "2021.1-SP7" (_flow fab_demo "2021.1-SP7"
(_comment "Generated by Fabric Compiler (version on 2021.1-SP7<build 86875>) at Thu Dec 14 21:56:34 2023")
(_comment "Generated by Fabric Compiler (version on 2021.1-SP7<build 86875>) at Fri Dec 15 09:34:17 2023")
(_version "1.0.5") (_version "1.0.5")
(_status "initial") (_status "initial")
(_project (_project
@ -39,7 +39,7 @@
) )
(_file "source/src/uart_reg_reader.v" (_file "source/src/uart_reg_reader.v"
(_format verilog) (_format verilog)
(_timespec "2023-12-14T20:47:29")
(_timespec "2023-12-15T09:32:26")
) )
(_file "source/src/monitor_line.v" (_file "source/src/monitor_line.v"
(_format verilog) (_format verilog)
@ -89,7 +89,7 @@
) )
(_file "source/test/test_uart_reg_reader.v" + "test_uart_reg_reader:" (_file "source/test/test_uart_reg_reader.v" + "test_uart_reg_reader:"
(_format verilog) (_format verilog)
(_timespec "2023-12-14T20:29:04")
(_timespec "2023-12-15T09:33:30")
) )
) )
) )
@ -100,17 +100,17 @@
(_db_output (_db_output
(_file "compile/Top_comp.adf" (_file "compile/Top_comp.adf"
(_format adif) (_format adif)
(_timespec "2023-12-14T21:55:55")
(_timespec "2023-12-15T09:33:46")
) )
) )
(_output (_output
(_file "compile/Top.cmr" (_file "compile/Top.cmr"
(_format verilog) (_format verilog)
(_timespec "2023-12-14T21:55:55")
(_timespec "2023-12-15T09:33:46")
) )
(_file "compile/cmr.db" (_file "compile/cmr.db"
(_format text) (_format text)
(_timespec "2023-12-14T21:55:55")
(_timespec "2023-12-15T09:33:46")
) )
) )
) )
@ -126,21 +126,21 @@
(_db_output (_db_output
(_file "synthesize/Top_syn.adf" (_file "synthesize/Top_syn.adf"
(_format adif) (_format adif)
(_timespec "2023-12-14T21:55:58")
(_timespec "2023-12-15T09:33:49")
) )
) )
(_output (_output
(_file "synthesize/Top_syn.vm" (_file "synthesize/Top_syn.vm"
(_format structural_verilog) (_format structural_verilog)
(_timespec "2023-12-14T21:55:58")
(_timespec "2023-12-15T09:33:49")
) )
(_file "synthesize/Top.snr" (_file "synthesize/Top.snr"
(_format text) (_format text)
(_timespec "2023-12-14T21:55:58")
(_timespec "2023-12-15T09:33:50")
) )
(_file "synthesize/snr.db" (_file "synthesize/snr.db"
(_format text) (_format text)
(_timespec "2023-12-14T21:55:58")
(_timespec "2023-12-15T09:33:50")
) )
) )
) )
@ -161,21 +161,21 @@
(_db_output (_db_output
(_file "device_map/Top_map.adf" (_file "device_map/Top_map.adf"
(_format adif) (_format adif)
(_timespec "2023-12-14T21:56:00")
(_timespec "2023-12-15T09:33:56")
) )
) )
(_output (_output
(_file "device_map/Top_dmr.prt" (_file "device_map/Top_dmr.prt"
(_format text) (_format text)
(_timespec "2023-12-14T21:56:00")
(_timespec "2023-12-15T09:33:56")
) )
(_file "device_map/Top.dmr" (_file "device_map/Top.dmr"
(_format text) (_format text)
(_timespec "2023-12-14T21:56:00")
(_timespec "2023-12-15T09:33:56")
) )
(_file "device_map/dmr.db" (_file "device_map/dmr.db"
(_format text) (_format text)
(_timespec "2023-12-14T21:56:00")
(_timespec "2023-12-15T09:33:56")
) )
) )
) )
@ -184,7 +184,7 @@
(_input (_input
(_file "device_map/led_test.pcf" (_file "device_map/led_test.pcf"
(_format pcf) (_format pcf)
(_timespec "2023-12-14T21:56:00")
(_timespec "2023-12-15T09:33:56")
) )
) )
) )
@ -198,33 +198,33 @@
(_db_output (_db_output
(_file "place_route/Top_pnr.adf" (_file "place_route/Top_pnr.adf"
(_format adif) (_format adif)
(_timespec "2023-12-14T21:56:20")
(_timespec "2023-12-15T09:34:12")
) )
) )
(_output (_output
(_file "place_route/Top.prr" (_file "place_route/Top.prr"
(_format text) (_format text)
(_timespec "2023-12-14T21:56:20")
(_timespec "2023-12-15T09:34:12")
) )
(_file "place_route/Top_prr.prt" (_file "place_route/Top_prr.prt"
(_format text) (_format text)
(_timespec "2023-12-14T21:56:20")
(_timespec "2023-12-15T09:34:12")
) )
(_file "place_route/clock_utilization.txt" (_file "place_route/clock_utilization.txt"
(_format text) (_format text)
(_timespec "2023-12-14T21:56:20")
(_timespec "2023-12-15T09:34:12")
) )
(_file "place_route/Top_plc.adf" (_file "place_route/Top_plc.adf"
(_format adif) (_format adif)
(_timespec "2023-12-14T21:56:14")
(_timespec "2023-12-15T09:34:05")
) )
(_file "place_route/Top_pnr.netlist" (_file "place_route/Top_pnr.netlist"
(_format text) (_format text)
(_timespec "2023-12-14T21:56:20")
(_timespec "2023-12-15T09:34:12")
) )
(_file "place_route/prr.db" (_file "place_route/prr.db"
(_format text) (_format text)
(_timespec "2023-12-14T21:56:21")
(_timespec "2023-12-15T09:34:13")
) )
) )
) )
@ -240,17 +240,17 @@
(_db_output (_db_output
(_file "report_timing/Top_rtp.adf" (_file "report_timing/Top_rtp.adf"
(_format adif) (_format adif)
(_timespec "2023-12-14T21:56:24")
(_timespec "2023-12-15T09:34:16")
) )
) )
(_output (_output
(_file "report_timing/Top.rtr" (_file "report_timing/Top.rtr"
(_format text) (_format text)
(_timespec "2023-12-14T21:56:24")
(_timespec "2023-12-15T09:34:16")
) )
(_file "report_timing/rtr.db" (_file "report_timing/rtr.db"
(_format text) (_format text)
(_timespec "2023-12-14T21:56:25")
(_timespec "2023-12-15T09:34:17")
) )
) )
) )
@ -270,25 +270,7 @@
) )
(_task tsk_gen_bitstream (_task tsk_gen_bitstream
(_command cmd_gen_bitstream (_command cmd_gen_bitstream
(_gci_state (_integer 2))
(_output
(_file "generate_bitstream/Top.sbit"
(_format text)
(_timespec "2023-12-14T21:56:33")
)
(_file "generate_bitstream/Top.smsk"
(_format text)
(_timespec "2023-12-14T21:56:33")
)
(_file "generate_bitstream/Top.bgr"
(_format text)
(_timespec "2023-12-14T21:56:33")
)
(_file "generate_bitstream/bgr.db"
(_format text)
(_timespec "2023-12-14T21:56:34")
)
)
(_gci_state (_integer 0))
) )
) )
) )

66
source/src/uart_reg_reader.v
View File

@ -5,7 +5,7 @@ module uart_reg_reader #(
input clk, //clock input input clk, //clock input
input rst_n, //asynchronous reset input, low active input rst_n, //asynchronous reset input, low active
input wire [31:0] reg_data, //received serial data input wire [31:0] reg_data, //received serial data
output reg [ 7:0] reg_add,
output reg [31:0] reg_add,
output reg reg_add_valid, output reg reg_add_valid,
input wire uart_rx_pin, input wire uart_rx_pin,
output wire uart_tx_pin output wire uart_tx_pin
@ -21,27 +21,24 @@ module uart_reg_reader #(
// //
// //
// //
parameter STATE_IDLE = 0; parameter STATE_IDLE = 0;
parameter STATE_READ_REG_ADD = 1; parameter STATE_READ_REG_ADD = 1;
parameter STATE_READ_REG = 2; parameter STATE_READ_REG = 2;
parameter STATE_SEND_REG_DATA = 3; parameter STATE_SEND_REG_DATA = 3;
parameter STATE_WAIT_SEND_END = 4; parameter STATE_WAIT_SEND_END = 4;
wire [7:0] rx_data; wire [7:0] rx_data;
wire rx_data_valid; wire rx_data_valid;
wire rx_data_ready; wire rx_data_ready;
wire tx_data_ready; wire tx_data_ready;
reg [7:0] tx_data;
reg tx_data_valid;
reg [7:0] tx_data = 0;
reg tx_data_valid = 0;
reg [7:0] state;
reg [7:0] rxpacket_num;
reg [7:0] txpacket_num;
reg [7:0] rxdatacache; //接收数据buffer
reg [7:0] state = 0;
reg [7:0] rxpacket_num = 0;
reg [7:0] txpacket_num = 0;
reg [7:0] rxdatacache = 0; //接收数据buffer
uart_rx #( uart_rx #(
.CLK_FRE (CLK_FRE), .CLK_FRE (CLK_FRE),
@ -69,20 +66,24 @@ module uart_reg_reader #(
assign rx_data_ready = 1'b1; assign rx_data_ready = 1'b1;
reg [ 7:0] substep = 0;
reg [31:0] reg_data_cache = 0;
reg [3:0] txdatastep = 0;
always @(posedge clk or negedge rst_n) begin always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin if (!rst_n) begin
state <= STATE_IDLE; state <= STATE_IDLE;
rxpacket_num <= 0; rxpacket_num <= 0;
txpacket_num <= 0; txpacket_num <= 0;
txdatastep <= 0;
substep <= 0;
reg_add <= 0;
reg_add_valid <= 0;
end else begin end else begin
case (state) case (state)
STATE_IDLE: begin STATE_IDLE: begin
rxpacket_num <= 0; rxpacket_num <= 0;
txpacket_num <= 0; txpacket_num <= 0;
txdatastep <= 0;
substep <= 0;
state <= STATE_READ_REG_ADD; state <= STATE_READ_REG_ADD;
end end
STATE_READ_REG_ADD: begin STATE_READ_REG_ADD: begin
@ -94,26 +95,53 @@ module uart_reg_reader #(
end end
end end
STATE_READ_REG: begin STATE_READ_REG: begin
case (substep)
0: begin
reg_add_valid <= 1;
reg_add[7:0] <= rxdatacache;
substep <= 1;
end
1: begin
tx_data_valid <= 0;
substep <= 0;
state <= STATE_SEND_REG_DATA; state <= STATE_SEND_REG_DATA;
end end
endcase
end
STATE_SEND_REG_DATA: begin STATE_SEND_REG_DATA: begin
case (txdatastep)
case (substep)
0: begin 0: begin
tx_data <= rxdatacache;
case (txpacket_num)
0: begin
tx_data[7:0] <= reg_data_cache[7:0];
end
1: begin
tx_data[7:0] <= reg_data_cache[15:8];
end
2: begin
tx_data[7:0] <= reg_data_cache[23:16];
end
3: begin
tx_data[7:0] <= reg_data_cache[31:24];
end
default: begin
tx_data[7:0] <= 0;
end
endcase
tx_data_valid <= 1; tx_data_valid <= 1;
txpacket_num <= txpacket_num + 1; txpacket_num <= txpacket_num + 1;
txdatastep <= 1;
substep <= 1;
end end
1: begin 1: begin
tx_data_valid <= 0; tx_data_valid <= 0;
txdatastep <= 2;
substep <= 2;
end end
2: begin 2: begin
if (tx_data_ready) begin if (tx_data_ready) begin
if (txpacket_num != 4) begin if (txpacket_num != 4) begin
txdatastep <= 0;
substep <= 0;
end else begin end else begin
txdatastep <= 0;
substep <= 0;
state <= STATE_IDLE; state <= STATE_IDLE;
end end
end end

4
source/test/test_uart_reg_reader.v
View File

@ -5,7 +5,7 @@ module test_uart_reg_reader;
reg rst_n; reg rst_n;
reg [31:0] reg_data; reg [31:0] reg_data;
wire [7:0] reg_add;
wire [31:0] reg_add;
wire reg_add_valid; wire reg_add_valid;
reg uart_rx_pin; reg uart_rx_pin;
wire uart_tx_pin; wire uart_tx_pin;
@ -25,7 +25,7 @@ module test_uart_reg_reader;
// Initialize Inputs // Initialize Inputs
clk_50m = 0; clk_50m = 0;
rst_n = 0; rst_n = 0;
reg_data = 0;
reg_data = 31'h11223344;
uart_rx_pin = 1; uart_rx_pin = 1;
#10; #10;

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