`timescale 10ns / 10ns
module test_top;
  reg  sys_clk;
  reg  rst_n;

  wire core_board_debug_led;

  reg  spi2_cs_pin;
  reg  spi2_clk_pin;
  reg  spi2_tx_pin;
  wire spi2_rx_pin;

  wire sync_ttl_out1;
  wire sync_ttl_out1_state_led;

  wire sync_ttl_out2;
  wire sync_ttl_out2_state_led;

  wire sync_ttl_out3;
  wire sync_ttl_out3_state_led;

  wire sync_ttl_out4;
  wire sync_ttl_out4_state_led;

  initial begin
    spi2_cs_pin  = 1;
    spi2_clk_pin = 1;
    spi2_tx_pin  = 1;
  end


  task spi_write_reg;
    input [15:0] addr;
    input [31:0] data;
    integer i;
    begin
      addr[15] = 1;
      spi2_cs_pin = 0;
      #30;  // 100ns

      for (i = 0; i < 48; i = i + 1) begin
        spi2_clk_pin = 0;
        if (i <= 15) spi2_tx_pin = addr[i];
        else spi2_tx_pin = data[i-16];
        #30;
        spi2_clk_pin = 1;
        #30;
      end
      spi2_clk_pin = 0;
      #10;
      spi2_clk_pin = 1;

      #20;
      spi2_cs_pin = 1;
      spi2_tx_pin = 1;
      #300;
    end
  endtask


  Top top_impl (
      .sys_clk(sys_clk),
      .rst_n(rst_n),
      .core_board_debug_led(core_board_debug_led),

      .spi2_cs_pin (spi2_cs_pin),
      .spi2_clk_pin(spi2_clk_pin),
      .spi2_rx_pin (spi2_tx_pin),
      .spi2_tx_pin (spi2_rx_pin),

      .sync_ttl_out1(sync_ttl_out1),
      .sync_ttl_out1_state_led(sync_ttl_out1_state_led),
      .sync_ttl_out2(sync_ttl_out2),
      .sync_ttl_out2_state_led(sync_ttl_out2_state_led),
      .sync_ttl_out3(sync_ttl_out3),
      .sync_ttl_out3_state_led(sync_ttl_out3_state_led),
      .sync_ttl_out4(sync_ttl_out4),
      .sync_ttl_out4_state_led(sync_ttl_out4_state_led)

  );

  initial begin
    sys_clk = 0;
    rst_n   = 0;

    #100;
    rst_n = 1;

    #100;
    spi_write_reg(16'h0020, 32'h00000001);
    spi_write_reg(16'h0021, 32'h00000010);
    spi_write_reg(16'h0022, 32'h00000100);
    spi_write_reg(16'h0023, 32'h00001000);

    spi_write_reg(16'h0020, 32'h00000002);
    spi_write_reg(16'h0021, 32'h00000020);
    spi_write_reg(16'h0022, 32'h00000200);
    spi_write_reg(16'h0023, 32'h00002000);

    #100000000;
    $stop;
  end
  always #1 sys_clk = ~sys_clk;  // 50MHZ时钟
endmodule