`timescale 1ns / 1ns
module test_spi_reg_reader;
  // input clk,   
  // input rst_n, 

  // output reg  [31:0] addr,
  // output reg  [31:0] wr_data,
  // output reg         wr_en,
  // input  wire [31:0] rd_data,      

  // input  wire        spi_cs_pin,
  // input  wire        spi_clk_pin,
  // input  wire        spi_rx_pin,
  // output reg         spi_tx_pin

  reg         clk_50m;
  reg         rst_n;

  wire [31:0] addr;
  wire [31:0] wr_data;
  wire        wr_en;
  reg  [31:0] rd_data;

  reg         spi_cs_pin;
  reg         spi_clk_pin;
  reg         spi_rx_pin;
  wire        spi_tx_pin;




  spi_reg_reader spi_reg_reader_impl (
      .clk(clk_50m),
      .rst_n(rst_n),
      .addr(addr),
      .wr_data(wr_data),
      .wr_en(wr_en),
      .rd_data(rd_data),
      .spi_cs_pin(spi_cs_pin),
      .spi_clk_pin(spi_clk_pin),
      .spi_rx_pin(spi_rx_pin),
      .spi_tx_pin(spi_tx_pin)
  );

  //   reg         rst_n;
  //   reg  [31:0] rd_data;
  // reg         spi_tx_pin;
  //   reg clk_50m;
  //   reg spi_cs_pin;
  //   reg spi_clk_pin;
  //   reg spi_rx_pin;


  always #10 clk_50m = ~clk_50m;  //20ns 50MHZ
  integer i = 0;
  reg [63:0] txdata = 64'h11_22_33_44_55_66_77_88
  initial begin
    rst_n <= 0;
    clk_50m <= 0;
    spi_cs_pin <= 1;
    spi_clk_pin <= 1;
    spi_rx_pin <= 0;
    rd_data <= 32'h11223344;

    #100;
    rst_n <= 1;

    #100;
    spi_cs_pin <= 0;
    #100;

    repeat (64) begin
      spi_clk_pin <= 0;
      spi_rx_pin  <= txdata[i];
      #200;
      spi_clk_pin <= 1;
      i = i + 1;
      #200;
    end

    spi_clk_pin <= 0;
    #200;
    spi_clk_pin <= 1;
    #200;
    spi_cs_pin <= 1;

    #1000;
    $stop;
  end
endmodule