(_flow fab_demo "2021.1-SP7"
    (_comment "Generated by Fabric Compiler (version on 2021.1-SP7<build 86875>) at Mon Jan  8 15:22:43 2024")
    (_version "1.0.5")
    (_status "initial")
    (_project 
    )
    (_task tsk_setup
        (_widget wgt_select_arch
            (_input
                (_part
                    (_family Logos)
                    (_device PGL22G)
                    (_speedgrade -6)
                    (_package MBG324)
                )
            )
        )
        (_widget wgt_my_design_src
            (_input
                (_file "source/src/transmitter.v"
                    (_format verilog)
                    (_timespec "2023-12-14T15:23:21")
                )
                (_file "source/src/baud_rate_gen.v"
                    (_format verilog)
                    (_timespec "2023-12-13T15:21:23")
                )
                (_file "source/src/top.v" + "Top:"
                    (_format verilog)
                    (_timespec "2024-01-08T15:22:29")
                )
                (_file "source/src/uart_tx.v"
                    (_format verilog)
                    (_timespec "2017-08-01T15:37:24")
                )
                (_file "source/src/uart_rx.v"
                    (_format verilog)
                    (_timespec "2023-12-13T10:31:56")
                )
                (_file "source/src/uart_reg_reader.v"
                    (_format verilog)
                    (_timespec "2023-12-15T09:32:26")
                )
                (_file "source/src/monitor_line.v"
                    (_format verilog)
                    (_timespec "2023-12-14T21:44:03")
                )
                (_file "source/src/spi_reg_reader.v"
                    (_format verilog)
                    (_timespec "2024-01-08T15:19:56")
                )
                (_file "source/src/src_ttl_parser.v"
                    (_format verilog)
                    (_timespec "2024-01-08T14:55:25")
                )
                (_file "source/src/src_timecode.v"
                    (_format verilog)
                    (_timespec "2024-01-08T14:55:20")
                )
                (_file "source/src/zutils/zutils_pluse_generator.v"
                    (_format verilog)
                    (_timespec "2023-12-31T16:28:46")
                )
                (_file "source/src/zutils/zutils_edge_detecter.v"
                    (_format verilog)
                    (_timespec "2023-12-31T16:39:25")
                )
                (_file "source/src/zutils/zutils_register.v"
                    (_format verilog)
                    (_timespec "2024-01-08T14:54:46")
                )
                (_file "source/src/zutils/zutils_multiplexer_4t1.v"
                    (_format verilog)
                    (_timespec "2024-01-08T12:37:43")
                )
                (_file "source/src/zutils/zutils_debug_led.v"
                    (_format verilog)
                    (_timespec "2024-01-06T19:12:28")
                )
                (_file "source/src/zutils/zutils_signal_filter.v"
                    (_format verilog)
                    (_timespec "2024-01-07T18:57:38")
                )
                (_file "source/src/zutils/zutils_clk_parser.v"
                    (_format verilog)
                    (_timespec "2024-01-07T18:36:41")
                )
                (_file "source/src/zutils/zutils_multiplexer_16t1.v"
                    (_format verilog)
                    (_timespec "2024-01-08T12:43:05")
                )
                (_file "source/src/output/ttl_output.v"
                    (_format verilog)
                    (_timespec "2024-01-08T15:16:56")
                )
                (_file "source/src/zutils/zutils_pwm_generator.v"
                    (_format verilog)
                    (_timespec "2024-01-08T10:07:08")
                )
                (_file "source/src/rd_data_router.v"
                    (_format verilog)
                    (_timespec "2024-01-08T15:00:24")
                )
            )
        )
        (_widget wgt_my_ips_src
            (_input
                (_ip "ipcore/SPLL/SPLL.idf"
                    (_timespec "2024-01-07T14:25:26")
                    (_ip_source_item "ipcore/SPLL/SPLL.v"
                        (_timespec "2024-01-07T14:25:26")
                    )
                )
            )
        )
        (_widget wgt_import_logic_con_file
            (_input
                (_file "led_test.fdc"
                    (_format fdc)
                    (_timespec "2024-01-07T14:16:20")
                )
            )
        )
        (_widget wgt_edit_user_cons
            (_attribute _click_to_run (_switch ON))
        )
        (_widget wgt_simulation
            (_option compiled_lib_location (_string "pango_sim_libraries"))
            (_option verilog_options (_string ""))
            (_option gen_param (_string ""))
            (_option simulate_runtime (_string "10000ms"))
            (_option sim_exe_dir (_string "C:/modeltech64_10.5/win64"))
            (_input
                (_file "source/test/test_transmitter.v"
                    (_format verilog)
                    (_timespec "2023-12-13T19:33:40")
                )
                (_file "source/test/test_baud_rate_gen.v"
                    (_format verilog)
                    (_timespec "2023-12-13T19:30:23")
                )
                (_file "source/test/test_top.v" + "test_top:"
                    (_format verilog)
                    (_timespec "2024-01-07T19:04:55")
                )
                (_file "source/test/test_uart_reg_reader.v"
                    (_format verilog)
                    (_timespec "2023-12-15T22:18:26")
                )
                (_file "source/test/test_spi_reg_reader.v"
                    (_format verilog)
                    (_timespec "2023-12-15T22:10:16")
                )
            )
        )
    )
    (_task tsk_compile
        (_command cmd_compile
            (_gci_state (_integer 2))
            (_db_output
                (_file "compile/Top_comp.adf"
                    (_format adif)
                    (_timespec "2024-01-08T15:22:40")
                )
            )
            (_output
                (_file "compile/Top.cmr"
                    (_format verilog)
                    (_timespec "2024-01-08T15:22:39")
                )
                (_file "compile/cmr.db"
                    (_format text)
                    (_timespec "2024-01-08T15:22:40")
                )
            )
        )
        (_widget wgt_rtl_view
            (_attribute _click_to_run (_switch ON))
        )
    )
    (_task tsk_synthesis
        (_command cmd_synthesize
            (_gci_state (_integer 2))
            (_option ads (_switch ON))
            (_option selected_syn_tool_opt (_integer 2))
            (_db_output
                (_file "synthesize/Top_syn.adf"
                    (_format adif)
                    (_timespec "2024-01-08T15:22:43")
                )
            )
            (_output
                (_file "synthesize/Top_syn.vm"
                    (_format structural_verilog)
                    (_timespec "2024-01-08T15:22:43")
                )
                (_file "synthesize/Top.snr"
                    (_format text)
                    (_timespec "2024-01-08T15:22:43")
                )
                (_file "synthesize/snr.db"
                    (_format text)
                    (_timespec "2024-01-08T15:22:43")
                )
            )
        )
        (_widget wgt_tech_view
            (_attribute _click_to_run (_switch ON))
        )
        (_widget wgt_map_constraint
        )
        (_widget wgt_my_fic_src
        )
        (_widget wgt_inserter_gui_view
            (_attribute _click_to_run (_switch ON))
        )
    )
    (_task tsk_devmap
        (_command cmd_devmap
            (_gci_state (_integer 0))
        )
        (_widget wgt_edit_placement_cons
            (_attribute _click_to_run (_switch ON))
            (_input
                (_file "device_map/led_test.pcf"
                    (_format pcf)
                    (_timespec "2024-01-07T20:01:36")
                )
            )
        )
        (_widget wgt_edit_route_cons
            (_attribute _click_to_run (_switch ON))
        )
    )
    (_task tsk_pnr
        (_command cmd_pnr
            (_gci_state (_integer 0))
        )
        (_widget wgt_power_calculator
            (_attribute _click_to_run (_switch ON))
        )
        (_widget wgt_timing_analysis
            (_attribute _click_to_run (_switch ON))
        )
        (_command cmd_report_post_pnr_timing
            (_gci_state (_integer 0))
            (_attribute _auto_exe_lock (_switch OFF))
        )
        (_widget wgt_arch_browser
            (_attribute _click_to_run (_switch ON))
        )
        (_command cmd_report_power
            (_gci_state (_integer 0))
            (_attribute _auto_exe_lock (_switch OFF))
            (_attribute _auto_exe (_switch OFF))
        )
        (_command cmd_gen_netlist
            (_gci_state (_integer 0))
            (_attribute _auto_exe_lock (_switch OFF))
            (_attribute _auto_exe (_switch OFF))
        )
    )
    (_task tsk_gen_bitstream
        (_command cmd_gen_bitstream
            (_gci_state (_integer 0))
        )
    )
)