IP Generator (Version 2021.1-SP7 build 86875)
Check out license ...
Start generating at 2024-01-07 14:25
Instance: SPLL (D:\workspace\fpga_demo\led_test\ipcore\SPLL\SPLL.idf)
IP: PLL (1.5)
Part: Logos-PGL22G-MBG324--6
Create directory 'rtl' ...
Copy 'ipml_pll_wrapper_v1_4.v.xml' ...
Compile file 'ipml_pll_wrapper_v1_4.v.xml' to 'SPLL.v' ...
Found top module 'SPLL' in file 'SPLL.v'.
Copy 'ipml_pll_wrapper_v1_4_tb.v.xml' ...
Compile file 'ipml_pll_wrapper_v1_4_tb.v.xml' to 'SPLL_tb.v' ...
Create template file 'SPLL_tmpl.v' ...
Create template file 'SPLL_tmpl.vhdl' ...
There is 1 source file to synthesize.
Synthesis is disabled.
Done: 0 error(s), 0 warning(s)