`timescale 1ns / 1ns
module Top (
    input sys_clk,
    input rst_n,
    output reg [3:0] led,
    output reg [3:0] key,
    output wire usb_serial_tx,
    input wire usb_serial_rx,
    output wire [35:3] test_io
);
  wire inclkpll_clk0out;
  inclkpll inclkpll_inst (
      .clkin1 (sys_clk),
      .clkout0(inclkpll_clk0out)
  );

  uart_reg_reader uart_reg_reader_impl (
      .clk(sys_clk),
      .rst_n(rst_n),
      .reg_data(),
      .reg_add(),
      .reg_add_valid(),
      .uart_rx_pin(usb_serial_rx),
      .uart_tx_pin(usb_serial_tx)
  );

  monitor_line monitor_line_usb_serial_rx(sys_clk, rst_n, usb_serial_rx, test_io[4]);
  assign test_io[3] = usb_serial_tx;
//   assign test_io[3] = inclkpll_clk0out;


endmodule