`timescale 1ns / 1ns
module test_baud_rate_gen;
  // Inputs
  reg clk_50m;
  reg rst_n;

   wire rxclk_en;
   wire txclk_en;

  baud_rate_gen baud_rate_gen_impl (
      .clk_50m (clk_50m),
      .rxclk_en(rxclk_en),
      .txclk_en(txclk_en)
  );

  initial begin
    // Initialize Inputs
    clk_50m = 0;
    rst_n   = 0;

    #100;
    rst_n = 1;

    #15;

    #100000;
    $stop;
  end
  always #10 clk_50m = ~clk_50m;  //20ns 50MHZ
endmodule