`timescale 10ns / 10ns
module test_top;
  reg  sys_clk;
  reg  rst_n;

  wire core_board_debug_led;

  Top top_impl (
      .sys_clk(sys_clk),
      .rst_n(rst_n),
      .core_board_debug_led(core_board_debug_led)
  );

  initial begin
    sys_clk = 0;
    rst_n   = 0;

    #100;
    rst_n = 1;

    #15;

    // #5000000;
    // $stop;
  end
  always #1 sys_clk = ~sys_clk;  // 50MHZ时钟
endmodule