(_flow fab_demo "2021.1-SP7" (_comment "Generated by Fabric Compiler (version on 2021.1-SP7) at Sun Dec 31 15:14:14 2023") (_version "1.0.5") (_status "initial") (_project ) (_task tsk_setup (_widget wgt_select_arch (_input (_part (_family Logos) (_device PGL22G) (_speedgrade -6) (_package MBG324) ) ) ) (_widget wgt_my_design_src (_input (_file "source/src/transmitter.v" (_format verilog) (_timespec "2023-12-14T15:23:21") ) (_file "source/src/baud_rate_gen.v" (_format verilog) (_timespec "2023-12-13T15:21:23") ) (_file "source/src/top.v" + "Top:" (_format verilog) (_timespec "2023-12-31T15:13:50") ) (_file "source/src/uart_tx.v" (_format verilog) (_timespec "2017-08-01T15:37:24") ) (_file "source/src/uart_rx.v" (_format verilog) (_timespec "2023-12-13T10:31:56") ) (_file "source/src/uart_reg_reader.v" (_format verilog) (_timespec "2023-12-15T09:32:26") ) (_file "source/src/monitor_line.v" (_format verilog) (_timespec "2023-12-14T21:44:03") ) (_file "source/src/spi_reg_reader.v" (_format verilog) (_timespec "2023-12-15T22:06:08") ) (_file "source/src/src_ttl_parser.v" (_format verilog) (_timespec "2023-12-30T15:38:08") ) (_file "source/src/src_timecode.v" (_format verilog) (_timespec "2023-12-30T20:50:11") ) (_file "source/src/des_ttl_generator.v" (_format verilog) (_timespec "2023-12-31T15:12:53") ) (_file "source/src/zutils/zutils_pluse_generator.v" (_format verilog) (_timespec "2023-12-31T14:50:20") ) (_file "source/src/zutils/zutils_edge_detecter.v" (_format verilog) (_timespec "2023-12-31T15:00:01") ) (_file "source/src/zutils/zutils_register.v" (_format verilog) (_timespec "2023-12-31T14:53:25") ) ) ) (_widget wgt_my_ips_src (_input (_ip "ipcore/inclkpll/inclkpll.idf" (_timespec "2023-12-14T21:34:50") (_ip_source_item "ipcore/inclkpll/inclkpll.v" (_timespec "2023-12-14T21:34:50") ) ) (_ip "ipcore/ttl_pll/ttl_pll.idf" (_timespec "2023-12-30T15:00:33") ) ) ) (_widget wgt_import_logic_con_file (_input (_file "led_test.fdc" (_format fdc) (_timespec "2023-12-14T21:55:40") ) ) ) (_widget wgt_edit_user_cons (_attribute _click_to_run (_switch ON)) ) (_widget wgt_simulation (_option compiled_lib_location (_string "pango_sim_libraries")) (_option verilog_options (_string "")) (_option gen_param (_string "")) (_option simulate_runtime (_string "10000ms")) (_option sim_exe_dir (_string "C:/modeltech64_10.5/win64")) (_input (_file "source/test/test_transmitter.v" (_format verilog) (_timespec "2023-12-13T19:33:40") ) (_file "source/test/test_baud_rate_gen.v" (_format verilog) (_timespec "2023-12-13T19:30:23") ) (_file "source/test/test_top.v" (_format verilog) (_timespec "2023-12-13T21:56:53") ) (_file "source/test/test_uart_reg_reader.v" (_format verilog) (_timespec "2023-12-15T22:18:26") ) (_file "source/test/test_spi_reg_reader.v" + "test_spi_reg_reader:" (_format verilog) (_timespec "2023-12-15T22:10:16") ) ) ) ) (_task tsk_compile (_command cmd_compile (_gci_state (_integer 2)) (_db_output (_file "compile/Top_comp.adf" (_format adif) (_timespec "2023-12-31T15:14:05") ) ) (_output (_file "compile/Top.cmr" (_format verilog) (_timespec "2023-12-31T15:14:04") ) (_file "compile/cmr.db" (_format text) (_timespec "2023-12-31T15:14:05") ) ) ) (_widget wgt_rtl_view (_attribute _click_to_run (_switch ON)) ) ) (_task tsk_synthesis (_command cmd_synthesize (_gci_state (_integer 2)) (_option ads (_switch ON)) (_option selected_syn_tool_opt (_integer 2)) (_db_output (_file "synthesize/Top_syn.adf" (_format adif) (_timespec "2023-12-31T15:14:07") ) ) (_output (_file "synthesize/Top_syn.vm" (_format structural_verilog) (_timespec "2023-12-31T15:14:07") ) (_file "synthesize/Top.snr" (_format text) (_timespec "2023-12-31T15:14:07") ) (_file "synthesize/snr.db" (_format text) (_timespec "2023-12-31T15:14:07") ) ) ) (_widget wgt_tech_view (_attribute _click_to_run (_switch ON)) ) (_widget wgt_map_constraint ) (_widget wgt_my_fic_src ) (_widget wgt_inserter_gui_view (_attribute _click_to_run (_switch ON)) ) ) (_task tsk_devmap (_command cmd_devmap (_gci_state (_integer 2)) (_db_output (_file "device_map/Top_map.adf" (_format adif) (_timespec "2023-12-31T15:14:09") ) ) (_output (_file "device_map/Top_dmr.prt" (_format text) (_timespec "2023-12-31T15:14:09") ) (_file "device_map/Top.dmr" (_format text) (_timespec "2023-12-31T15:14:09") ) (_file "device_map/dmr.db" (_format text) (_timespec "2023-12-31T15:14:09") ) ) ) (_widget wgt_edit_placement_cons (_attribute _click_to_run (_switch ON)) (_input (_file "device_map/led_test.pcf" (_format pcf) (_timespec "2023-12-31T15:14:09") ) ) ) (_widget wgt_edit_route_cons (_attribute _click_to_run (_switch ON)) ) ) (_task tsk_pnr (_command cmd_pnr (_gci_state (_integer 2)) (_db_output (_file "place_route/Top_pnr.adf" (_format adif) (_timespec "2023-12-31T15:14:13") ) ) (_output (_file "place_route/Top.prr" (_format text) (_timespec "2023-12-31T15:14:13") ) (_file "place_route/Top_prr.prt" (_format text) (_timespec "2023-12-31T15:14:13") ) (_file "place_route/clock_utilization.txt" (_format text) (_timespec "2023-12-31T15:14:12") ) (_file "place_route/Top_plc.adf" (_format adif) (_timespec "2023-12-31T15:14:12") ) (_file "place_route/Top_pnr.netlist" (_format text) (_timespec "2023-12-31T15:14:13") ) (_file "place_route/prr.db" (_format text) (_timespec "2023-12-31T15:14:14") ) ) ) (_widget wgt_power_calculator (_attribute _click_to_run (_switch ON)) ) (_widget wgt_timing_analysis (_attribute _click_to_run (_switch ON)) ) (_command cmd_report_post_pnr_timing (_gci_state (_integer 0)) (_attribute _auto_exe_lock (_switch OFF)) ) (_widget wgt_arch_browser (_attribute _click_to_run (_switch ON)) ) (_command cmd_report_power (_gci_state (_integer 0)) (_attribute _auto_exe_lock (_switch OFF)) (_attribute _auto_exe (_switch OFF)) ) (_command cmd_gen_netlist (_gci_state (_integer 0)) (_attribute _auto_exe_lock (_switch OFF)) (_attribute _auto_exe (_switch OFF)) ) ) (_task tsk_gen_bitstream (_command cmd_gen_bitstream (_gci_state (_integer 0)) ) ) )