`timescale 1ns / 1ns
module Top (
    input sys_clk,
    input rst_n,
    output reg [3:0] led,
    output reg [3:0] key,
    output wire usb_serial_tx,
    input wire usb_serial_rx,
    output wire [35:3] test_io
);
  wire inclkpll_clk0out;
  inclkpll inclkpll_inst (
      .clkin1 (sys_clk),
      .clkout0(inclkpll_clk0out)
  );

des_ttl_generator des_ttl_generator_inst (
    .clk(sys_clk),
    .rst_n(rst_n),
    .addr(),
    .wr_data(0),
    .wr_en(0),
    .rd_data(),
    .signal_in(1),
    .ttloutput(test_io[3])
);


endmodule