`timescale 1ns / 1ns
module test_transmitter;
  // Inputs
  reg clk_50m;
  reg rst_n;


  reg [7:0] din;
  reg wr_en;
  wire tx;
  wire tx_busy;

  wire rxclk_en;
  wire txclk_en;


  baud_rate_gen baud_rate_gen_impl (
      .clk_50m (clk_50m),
      .rxclk_en(rxclk_en),
      .txclk_en(txclk_en)
  );

  transmitter transmitter_impl (
      .din(din),
      .wr_en(wr_en),
      .clk_50m(clk_50m),
      .clken(txclk_en),
      .tx(tx),
      .tx_busy(tx_busy)
  );

  initial begin
    // Initialize Inputs
    clk_50m = 0;
    rst_n   = 0;

    #10;
    rst_n = 1;

    #11;
    din   = 8'h55;
    wr_en = 1'b1;

    #15;
    wr_en = 0;

    #300000;
    $stop;
  end
  always #10 clk_50m = ~clk_50m;  //20ns 50MHZ
endmodule