// Created by IP Generator (Version 2021.1-SP7 build 86875) // Instantiation Template // // Insert the following codes into your Verilog file. // * Change the_instance_name to your own instance name. // * Change the signal names in the port associations SPLL the_instance_name ( .clkin1(clkin1), // input .pll_lock(pll_lock), // output .clkout0(clkout0), // output .clkout1(clkout1), // output .clkout2(clkout2) // output );