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13 lines
399 B
13 lines
399 B
// Created by IP Generator (Version 2021.1-SP7 build 86875)
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// Instantiation Template
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//
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// Insert the following codes into your Verilog file.
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// * Change the_instance_name to your own instance name.
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// * Change the signal names in the port associations
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inclkpll the_instance_name (
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.clkin1(clkin1), // input
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.pll_lock(pll_lock), // output
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.clkout0(clkout0) // output
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);
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