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30 lines
447 B
30 lines
447 B
`timescale 1ns / 1ns
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module test_baud_rate_gen;
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// Inputs
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reg clk_50m;
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reg rst_n;
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wire rxclk_en;
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wire txclk_en;
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baud_rate_gen baud_rate_gen_impl (
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.clk_50m (clk_50m),
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.rxclk_en(rxclk_en),
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.txclk_en(txclk_en)
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);
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initial begin
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// Initialize Inputs
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clk_50m = 0;
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rst_n = 0;
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#100;
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rst_n = 1;
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#15;
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#100000;
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$stop;
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end
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always #10 clk_50m = ~clk_50m; //20ns 50MHZ
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endmodule
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