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35 lines
691 B
35 lines
691 B
`timescale 1ns / 1ns
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//////////////////////////////////////////////////////////////////////////////////
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// Module Name: vtf_led_test
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//////////////////////////////////////////////////////////////////////////////////
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module vtf_led_test;
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// Inputs
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reg sys_clk;
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reg rst_n;
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// Outputs
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wire [3:0] led;
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// Instantiate the Unit Under Test (UUT)
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led_test uut (
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.sys_clk(sys_clk),
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.rst_n(rst_n),
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.led(led)
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);
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initial begin
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// Initialize Inputs
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sys_clk = 0;
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rst_n = 0;
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// Wait 100 ns for global reset to finish
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#1000;
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rst_n = 1;
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// Add stimulus here
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#20000;
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// $stop;
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end
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always #10 sys_clk = ~ sys_clk; //20ns
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endmodule
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