fpga_led_test

1.4 KiB

Raw Blame History

核心板引脚分配:

define_attribute {p:rst_n} {PAP_IO_DIRECTION} {INPUT}
define_attribute {p:rst_n} {PAP_IO_LOC} {U12}
define_attribute {p:rst_n} {PAP_IO_VCCIO} {3.3}
define_attribute {p:rst_n} {PAP_IO_STANDARD} {LVTTL33}

define_attribute {p:sys_clk} {PAP_IO_DIRECTION} {INPUT}
define_attribute {p:sys_clk} {PAP_IO_LOC} {B5}
define_attribute {p:sys_clk} {PAP_IO_VCCIO} {3.3}
define_attribute {p:sys_clk} {PAP_IO_STANDARD} {LVTTL33}

TTL OUTPUT
     1,2,3,4 丝印正确，正常输出

SIGNAL_GENERATOR
     启动方式:
          1.寄存器控制启动
          2.外部触发启动
          3.TIMECODE触发启动
     帧格式:
          TIMECODE:
               25/30/...
          GENLOCK:
               ....
     产生:
          1.start_state_sig (高电平表示拍照进行中)
          2.timecode_sig[64]
          3.timecode_tirgger_sig[1]
          4.genlock_sig[1] 帧信号,场信号
          5.秒信号


TTL_INPUT
TIMECODE_INPUT
TIMECODE_OUTPUT

GENLOCK_INPUT

1. 修改启动方式
2. 修改TIMECODE启动时间戳

TTL模块信号源输入
     0:0
     1:1
     2:ttl_input1_raw
     3:ttl_input1_division
     4:ttl_input2_raw
     5:ttl_input2_division
     6:ttl_input3_raw
     7:ttl_input3_division
     8:genlock_frame_freq
     9:timecode_trigger
    10:work_state_signal
    11:internal_frame_freq (genlock)
    12:internal_sec_freq

1.4 KiB Raw Blame History

1.4 KiB

Raw Blame History