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fpga_led_test
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fpga_led_test/source/src/top.v

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`timescale 1ns / 1ns
module Top (
input ex_clk,
input ex_rst_n,
/*******************************************************************************
* genlock *
*******************************************************************************/
input genlock_in_hsync,
input genlock_in_vsync,
input genlock_in_fsync,
output genlock_in_state_led,
/*******************************************************************************
* GENLOCK_OUTPUT *
*******************************************************************************/
output [9:0] genlock_out_dac,
output genlock_out_dac_clk,
output genlock_out_dac_state_led,
/*******************************************************************************
* TTL_IN *
*******************************************************************************/
input sync_ttl_in1,
output sync_ttl_in1_state_led,
input sync_ttl_in2,
output sync_ttl_in2_state_led,
input sync_ttl_in3,
output sync_ttl_in3_state_led,
input sync_ttl_in4,
output sync_ttl_in4_state_led,
/*******************************************************************************
* TTL_OUT *
*******************************************************************************/
output sync_ttl_out1,
output sync_ttl_out1_state_led,
output sync_ttl_out2,
output sync_ttl_out2_state_led,
output sync_ttl_out3,
output sync_ttl_out3_state_led,
output sync_ttl_out4,
output sync_ttl_out4_state_led,
/*******************************************************************************
* TIMECODE_IN *
*******************************************************************************/
input timecode_headphone_in,
output timecode_headphone_in_state_led,
input timecode_bnc_in,
output timecode_bnc_in_state_led,
/*******************************************************************************
* TIMECODE_OUTPUT *
*******************************************************************************/
output timecode_out_bnc,
output timecode_out_bnc_select,
output timecode_out_bnc_state_led,
output timecode_out_headphone,
output timecode_out_headphone_select,
output timecode_out_headphone_state_led,
/*******************************************************************************
* STM32_IF *
*******************************************************************************/
output stm32if_start_signal_out,
output stm32if_camera_sync_out,
output stm32if_timecode_sync_out,
//SPI 串行总线1
input wire spi1_cs_pin,
input wire spi1_clk_pin,
input wire spi1_rx_pin,
output wire spi1_tx_pin,
//SPI 串行总线2
input wire spi2_cs_pin,
input wire spi2_clk_pin,
input wire spi2_rx_pin,
output wire spi2_tx_pin,
/*******************************************************************************
* debug_signal_output *
*******************************************************************************/
output [15:0] debug_signal_output,
/*******************************************************************************
* CODE_BOARD *
*******************************************************************************/
output wire core_board_debug_led
);
localparam HARDWARE_TEST_MODE = 1;
//STM32寄存器地址
localparam REG_ADD_OFF_STM32 = 16'h0000;
localparam REG_ADD_OFF_FPGA_TEST = 16'h00020;
//控制中心寄存器地址
localparam REG_ADD_OFF_XSYNC_INTERNAL_SIG_GENERATOR = 16'h00030; // 48
//输入组件
localparam REG_ADD_OFF_TTLIN1 = 16'h0100;
localparam REG_ADD_OFF_TTLIN2 = 16'h0110;
localparam REG_ADD_OFF_TTLIN3 = 16'h0120;
localparam REG_ADD_OFF_TTLIN4 = 16'h0130;
localparam REG_ADD_OFF_TIMECODE_IN = 16'h0140;
localparam REG_ADD_OFF_GENLOCK_IN = 16'h0150;
//输出组件
localparam REG_ADD_OFF_TTLOUT1 = 16'h0200;
localparam REG_ADD_OFF_TTLOUT2 = 16'h0210;
localparam REG_ADD_OFF_TTLOUT3 = 16'h0220;
localparam REG_ADD_OFF_TTLOUT4 = 16'h0230;
localparam REG_ADD_OFF_TIMECODE_OUT = 16'h0240;
localparam REG_ADD_OFF_GENLOCK_OUT = 16'h0250;
localparam REG_ADD_OFF_STM32_IF = 16'h0260;
//调试组件
localparam REG_ADD_OFF_DEBUGER = 16'h0300;
SPLL spll (
.clkin1(ex_clk), // input
.pll_lock(pll_lock), // output
.clkout0(sys_clk_25m), // output
.clkout1(sys_clk_10m), // output
.clkout2(sys_clk_5m) // output
);
assign sys_clk = sys_clk_10m;
assign sys_rst_n = ex_rst_n & pll_lock;
localparam SYS_CLOCK_FREQ = 10000000;
// zutils_reset_sig_gen reset_sig_gen_inst (
// .clk(sys_clk),
// .rst_n(rst_n),
// .rst_n_out(sys_rst_n)
// );
/*******************************************************************************
* DEBUG_LED *
*******************************************************************************/
// zutils_debug_led #(
// .PERIOD_COUNT(10000000)
// ) core_board_debug_led_inst (
// .clk(sys_clk),
// .rst_n(sys_rst_n),
// .debug_led(core_board_debug_led)
// );
/*******************************************************************************
* SPIREADER *
*******************************************************************************/
wire [31:0] reg_reader_bus_addr;
wire [31:0] reg_reader_bus_wr_data;
wire reg_reader_bus_wr_en;
wire [31:0] reg_reader_bus_rd_data;
spi_reg_reader spi_reg_reader_inst (
.clk (sys_clk),
.rst_n(sys_rst_n),
.addr(reg_reader_bus_addr),
.wr_data(reg_reader_bus_wr_data),
.wr_en(reg_reader_bus_wr_en),
.rd_data(reg_reader_bus_rd_data),
//
.spi_cs_pin(spi2_cs_pin),
.spi_clk_pin(spi2_clk_pin),
.spi_rx_pin(spi2_rx_pin),
.spi_tx_pin(spi2_tx_pin)
);
wire [31:0] stm32_rd_data; //
wire [31:0] fpga_test_rd_data; //
wire [31:0] xsync_internal_sig_generator_rd_data;
wire [31:0] ttlin1_rd_data;
wire [31:0] ttlin2_rd_data;
wire [31:0] ttlin3_rd_data;
wire [31:0] ttlin4_rd_data;
wire [31:0] timecode_in_rd_data;
wire [31:0] genlock_in_rd_data;
wire [31:0] ttlout1_rd_data;
wire [31:0] ttlout2_rd_data;
wire [31:0] ttlout3_rd_data;
wire [31:0] ttlout4_rd_data;
wire [31:0] timecode_out_rd_data;
wire [31:0] genlock_out_rd_data;
wire [31:0] stm32_if_rd_data;
wire [31:0] debuger_rd_data;
/*******************************************************************************
* TEST_SPI_REG *
*******************************************************************************/
zutils_register16 #(
.REG_START_ADD(REG_ADD_OFF_FPGA_TEST),
.REG0_INIT(31'h0000_0000_0000_0001),
.REG1_INIT(31'h0000_0000_0000_0010),
.REG2_INIT(31'h0000_0000_0000_0100),
.REG3_INIT(31'h0000_0000_0000_1000),
.REG4_INIT(31'h0000_0000_0001_0000),
.REG5_INIT(31'h0000_0000_0010_0000),
.REG6_INIT(31'h0000_0000_0100_0000),
.REG7_INIT(31'h0000_0000_1000_0000),
.REG8_INIT(31'h0000_0001_0000_0000),
.REG9_INIT(31'h0000_0010_0000_0000),
.REGA_INIT(31'h0000_0100_0000_0000),
.REGB_INIT(31'h0000_1000_0000_0000),
.REGC_INIT(31'h0001_0000_0000_0000),
.REGD_INIT(31'h0010_0000_0000_0000),
.REGE_INIT(31'h0100_0000_0000_0000),
.REGF_INIT(31'h1000_0000_0000_0000)
) test_reg (
.clk(sys_clk),
.rst_n(sys_rst_n),
.addr(reg_reader_bus_addr),
.wr_data(reg_reader_bus_wr_data),
.wr_en(reg_reader_bus_wr_en),
.rd_data(fpga_test_rd_data)
);
/*******************************************************************************
* 信号源 *
*******************************************************************************/
wire ISIG_logic0; // 逻辑0
wire ISIG_logic1; // 逻辑1
wire ISIG_ttlin1_module_ext; // ttl1输入模块原始信号
wire ISIG_ttlin1_module_divide; // ttl1输入模块分频信号
wire ISIG_ttlin2_module_ext; // ttl2输入模块原始信号
wire ISIG_ttlin2_module_divide; // ttl2输入模块分频信号
wire ISIG_ttlin3_module_ext; // ttl3输入模块原始信号
wire ISIG_ttlin3_module_divide; // ttl3输入模块分频信号
wire ISIG_ttlin4_module_ext; // ttl4输入模块原始信号
wire ISIG_ttlin4_module_divide; // ttl4输入模块分频信号
wire ISIG_internal_en_flag; // 内部使能状态信号输出
wire ISIG_genlock_frame_sync_ext; // 外部genlock帧同步信号
wire ISIG_genlock_frame_sync_internal; // 内部genlock帧同步信号
wire ISIG_timecode_frame_sync_ext; // 外部timecode帧同步信号
wire ISIG_timecode_frame_sync_internal; // 内部timecode帧同步信号
wire ISIG_timecode_serial_data_ext; // 外部timecode串行数据输入
wire ISIG_timecode_serial_data_internal; // 内部timecode串行数据输入
wire ISIG_internal_100hz; // 100hz测试信号
wire [63:0] ISIGBUS64_timecode_data_ext;
wire [31:0] ISIGBUS32_timecode_format_ext;
wire [63:0] ISIGBUS64_timecode_data_internal;
wire [31:0] ISIGBUS32_timecode_format_internal;
assign ISIG_genlock_frame_sync_ext = genlock_in_vsync;
assign ISIG_logic0 = 0;
assign ISIG_logic1 = 1;
/*******************************************************************************
* TTL输出模块信号源分配 *
*******************************************************************************/
wire [31:0] ttl_output_module_source_sig_af;
assign ttl_output_module_source_sig_af[0] = ISIG_logic0;
assign ttl_output_module_source_sig_af[1] = ISIG_logic1;
assign ttl_output_module_source_sig_af[2] = ISIG_ttlin1_module_ext;
assign ttl_output_module_source_sig_af[3] = ISIG_ttlin1_module_divide;
assign ttl_output_module_source_sig_af[4] = ISIG_ttlin2_module_ext;
assign ttl_output_module_source_sig_af[5] = ISIG_ttlin2_module_divide;
assign ttl_output_module_source_sig_af[6] = ISIG_ttlin3_module_ext;
assign ttl_output_module_source_sig_af[7] = ISIG_ttlin3_module_divide;
assign ttl_output_module_source_sig_af[8] = ISIG_ttlin4_module_ext;
assign ttl_output_module_source_sig_af[9] = ISIG_ttlin4_module_divide;
assign ttl_output_module_source_sig_af[10] = ISIG_internal_en_flag;
assign ttl_output_module_source_sig_af[11] = ISIG_genlock_frame_sync_ext;
assign ttl_output_module_source_sig_af[12] = ISIG_genlock_frame_sync_internal;
assign ttl_output_module_source_sig_af[13] = ISIG_timecode_frame_sync_ext;
assign ttl_output_module_source_sig_af[14] = ISIG_timecode_frame_sync_internal;
assign ttl_output_module_source_sig_af[15] = ISIG_timecode_serial_data_ext;
assign ttl_output_module_source_sig_af[16] = ISIG_timecode_serial_data_internal;
assign ttl_output_module_source_sig_af[31] = ISIG_internal_100hz;
xsync_internal_generator #(
.REG_START_ADD (REG_ADD_OFF_XSYNC_INTERNAL_SIG_GENERATOR),
.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ)
) xsync_internal_generator_ins (
.clk(sys_clk),
.rst_n(sys_rst_n),
.addr(reg_reader_bus_addr),
.wr_data(reg_reader_bus_wr_data),
.wr_en(reg_reader_bus_wr_en),
.rd_data(xsync_internal_sig_generator_rd_data),
.ext_ttlin1_module_raw_sig(ISIG_ttlin1_module_ext),
.ext_ttlin2_module_raw_sig(ISIG_ttlin2_module_ext),
.ext_ttlin3_module_raw_sig(ISIG_ttlin3_module_ext),
.ext_ttlin4_module_raw_sig(ISIG_ttlin4_module_ext),
.ext_timecode_tigger_sig(ISIG_timecode_frame_sync_ext),
.ext_timecode_data(ISIGBUS64_timecode_data_ext),
.ext_genlock_signal(ISIG_genlock_frame_sync_ext),
.out_timecode_tirgger_sig(ISIG_timecode_frame_sync_internal), //输出时码译码有效信号
.out_timecode_sig(ISIGBUS64_timecode_data_internal), //[63:0] 输出时间
.out_timecode_serial_sig(ISIG_timecode_serial_data_internal), //TIMECODE串行数据输出
.out_genlock_sig(ISIG_genlock_frame_sync_internal),
.out_en_flag(ISIG_internal_en_flag)
);
/*******************************************************************************
* ISIG_internal_100hz信号生成 *
*******************************************************************************/
zutils_pwm_generator #(
.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ),
.OUTPUT_FREQ(100)
) pwm100hz_gen (
.clk(sys_clk),
.rst_n(sys_rst_n),
.output_signal(ISIG_internal_100hz)
);
// ===========================================================================================================
// 输出组件
// ===========================================================================================================
/*******************************************************************************
* STM32_IF *
*******************************************************************************/
assign stm32if_start_signal_out = ISIG_internal_en_flag;
/*******************************************************************************
* timecode_output *
*******************************************************************************/
timecode_output #(
.REG_START_ADD (REG_ADD_OFF_TIMECODE_OUT),
.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ)
) timecode_output_inst (
.clk (sys_clk),
.rst_n(sys_rst_n),
.addr(reg_reader_bus_addr),
.wr_data(reg_reader_bus_wr_data),
.wr_en(reg_reader_bus_wr_en),
.rd_data(timecode_out_rd_data),
.ext_timecode_data(ISIGBUS64_timecode_data_ext), //63:0
.ext_timecode_format(ISIGBUS32_timecode_format_ext), //31:0
.ext_timecode_tigger_sig(ISIG_timecode_frame_sync_ext),
.ext_timecode_serial_data(ISIG_timecode_serial_data_ext),
.internal_timecode_data(ISIGBUS64_timecode_data_internal), //63:0
.internal_timecode_format(ISIGBUS32_timecode_format_internal), //31:0
.internal_timecode_tigger_sig(ISIG_timecode_frame_sync_internal),
.internal_timecode_serial_data(ISIG_timecode_serial_data_internal),
.stm32if_timecode_tigger_sig(stm32if_timecode_sync_out),
.timecode_out_bnc(timecode_out_bnc),
.timecode_out_bnc_select(timecode_out_bnc_select),
.timecode_out_bnc_state_led(timecode_out_bnc_state_led),
.timecode_out_headphone(timecode_out_headphone),
.timecode_out_headphone_select(timecode_out_headphone_select),
.timecode_out_headphone_state_led(timecode_out_headphone_state_led)
);
/*******************************************************************************
* TTL_OUTPUT *
*******************************************************************************/
ttl_output #(
.REG_START_ADD(REG_ADD_OFF_TTLOUT1),
.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ),
.ID(1)
) ttl_output_1 (
.clk (sys_clk),
.rst_n(sys_rst_n),
.addr(reg_reader_bus_addr),
.wr_data(reg_reader_bus_wr_data),
.wr_en(reg_reader_bus_wr_en),
.rd_data(ttlout1_rd_data),
.signal_in(ttl_output_module_source_sig_af),
.ttloutput(sync_ttl_out1),
.ttloutput_state_led(sync_ttl_out1_state_led)
);
ttl_output #(
.REG_START_ADD(REG_ADD_OFF_TTLOUT2),
.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ),
.ID(2)
) ttl_output_2 (
.clk (sys_clk),
.rst_n(sys_rst_n),
.addr(reg_reader_bus_addr),
.wr_data(reg_reader_bus_wr_data),
.wr_en(reg_reader_bus_wr_en),
.rd_data(ttlout2_rd_data),
.signal_in(ttl_output_module_source_sig_af),
.ttloutput(sync_ttl_out2),
.ttloutput_state_led(sync_ttl_out2_state_led)
);
ttl_output #(
.REG_START_ADD(REG_ADD_OFF_TTLOUT3),
.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ),
.ID(3)
) ttl_output_3 (
.clk (sys_clk),
.rst_n(sys_rst_n),
.addr(reg_reader_bus_addr),
.wr_data(reg_reader_bus_wr_data),
.wr_en(reg_reader_bus_wr_en),
.rd_data(ttlout3_rd_data),
.signal_in(ttl_output_module_source_sig_af),
.ttloutput(sync_ttl_out3),
.ttloutput_state_led(sync_ttl_out3_state_led)
);
ttl_output #(
.REG_START_ADD(REG_ADD_OFF_TTLOUT4),
.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ),
.ID(4)
) ttl_output_4 (
.clk (sys_clk),
.rst_n(sys_rst_n),
.addr(reg_reader_bus_addr),
.wr_data(reg_reader_bus_wr_data),
.wr_en(reg_reader_bus_wr_en),
.rd_data(ttlout4_rd_data),
.signal_in(ttl_output_module_source_sig_af),
.ttloutput(sync_ttl_out4),
.ttloutput_state_led(sync_ttl_out4_state_led)
);
rd_data_router #(
.REG_ADD_OFF_STM32(REG_ADD_OFF_STM32),
.REG_ADD_OFF_FPGA_TEST(REG_ADD_OFF_FPGA_TEST),
.REG_ADD_OFF_XSYNC_INTERNAL_SIG_GENERATOR(REG_ADD_OFF_XSYNC_INTERNAL_SIG_GENERATOR),
.REG_ADD_OFF_TTLIN1(REG_ADD_OFF_TTLIN1),
.REG_ADD_OFF_TTLIN2(REG_ADD_OFF_TTLIN2),
.REG_ADD_OFF_TTLIN3(REG_ADD_OFF_TTLIN3),
.REG_ADD_OFF_TTLIN4(REG_ADD_OFF_TTLIN4),
.REG_ADD_OFF_TIMECODE_IN(REG_ADD_OFF_TIMECODE_IN),
.REG_ADD_OFF_GENLOCK_IN(REG_ADD_OFF_GENLOCK_IN),
.REG_ADD_OFF_TTLOUT1(REG_ADD_OFF_TTLOUT1),
.REG_ADD_OFF_TTLOUT2(REG_ADD_OFF_TTLOUT2),
.REG_ADD_OFF_TTLOUT3(REG_ADD_OFF_TTLOUT3),
.REG_ADD_OFF_TTLOUT4(REG_ADD_OFF_TTLOUT4),
.REG_ADD_OFF_TIMECODE_OUT(REG_ADD_OFF_TIMECODE_OUT),
.REG_ADD_OFF_GENLOCK_OUT(REG_ADD_OFF_GENLOCK_OUT),
.REG_ADD_OFF_STM32_IF(REG_ADD_OFF_STM32_IF),
.REG_ADD_OFF_DEBUGER(REG_ADD_OFF_DEBUGER)
) rd_data_router_inst (
.addr(reg_reader_bus_addr),
.stm32_rd_data(stm32_rd_data),
.fpga_test_rd_data(fpga_test_rd_data),
.xsync_internal_sig_generator_rd_data(xsync_internal_sig_generator_rd_data),
.ttlin1_rd_data(ttlin1_rd_data),
.ttlin2_rd_data(ttlin2_rd_data),
.ttlin3_rd_data(ttlin3_rd_data),
.ttlin4_rd_data(ttlin4_rd_data),
.timecode_in_rd_data(timecode_in_rd_data),
.genlock_in_rd_data(genlock_in_rd_data),
.ttlout1_rd_data(ttlout1_rd_data), // ok
.ttlout2_rd_data(ttlout2_rd_data), // ok
.ttlout3_rd_data(ttlout3_rd_data), // ok
.ttlout4_rd_data(ttlout4_rd_data), // ok
.timecode_out_rd_data(timecode_out_rd_data),
.genlock_out_rd_data(genlock_out_rd_data),
.stm32_if_rd_data(stm32_if_rd_data),
.debuger_rd_data(debuger_rd_data),
.rd_data_out(reg_reader_bus_rd_data)
);
// assign reg_reader_bus_rd_data[31:0] = fpga_test_rd_data[31:0];
// output reg stm32if_timecode_tigger_sig,
// output reg timecode_out_bnc,
// output reg timecode_out_bnc_select, // 电平选择 0line,1:mic
// output reg timecode_out_bnc_state_led,
// output reg timecode_out_headphone,
// output reg timecode_out_headphone_select, // 电平选择 0line,1:mic
// output reg timecode_out_headphone_state_led
assign debug_signal_output[0] = spi2_cs_pin;
assign debug_signal_output[1] = spi2_clk_pin;
assign debug_signal_output[2] = spi2_rx_pin;
assign debug_signal_output[3] = spi2_tx_pin;
assign debug_signal_output[4] = sync_ttl_out1;
assign debug_signal_output[5] = sync_ttl_out2;
assign debug_signal_output[6] = sync_ttl_out3;
assign debug_signal_output[7] = sync_ttl_out4;
assign debug_signal_output[8] = stm32if_timecode_sync_out;
assign debug_signal_output[9] = timecode_out_bnc;
assign debug_signal_output[10] = timecode_out_headphone;
assign debug_signal_output[11] = timecode_out_bnc_select;
assign debug_signal_output[12] = timecode_out_headphone_select;
assign debug_signal_output[13] = 0;
assign debug_signal_output[14] = 0;
assign debug_signal_output[15] = 0;
assign core_board_debug_led = 1;
endmodule