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587 lines
22 KiB
587 lines
22 KiB
`timescale 1ns / 1ns
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module Top (
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input ex_clk,
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input ex_rst_n,
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/*******************************************************************************
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* genlock *
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*******************************************************************************/
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input genlock_in_hsync,
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input genlock_in_vsync,
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input genlock_in_fsync,
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output genlock_in_state_led,
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/*******************************************************************************
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* GENLOCK_OUTPUT *
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*******************************************************************************/
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output [9:0] genlock_out_dac,
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output genlock_out_dac_clk,
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output genlock_out_dac_state_led,
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/*******************************************************************************
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* TTL_IN *
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*******************************************************************************/
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input sync_ttl_in1,
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output sync_ttl_in1_state_led,
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input sync_ttl_in2,
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output sync_ttl_in2_state_led,
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input sync_ttl_in3,
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output sync_ttl_in3_state_led,
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input sync_ttl_in4,
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output sync_ttl_in4_state_led,
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/*******************************************************************************
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* TTL_OUT *
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*******************************************************************************/
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output sync_ttl_out1,
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output sync_ttl_out1_state_led,
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output sync_ttl_out2,
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output sync_ttl_out2_state_led,
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output sync_ttl_out3,
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output sync_ttl_out3_state_led,
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output sync_ttl_out4,
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output sync_ttl_out4_state_led,
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/*******************************************************************************
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* TIMECODE_IN *
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*******************************************************************************/
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input timecode_headphone_in,
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output timecode_headphone_in_state_led,
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input timecode_bnc_in,
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output timecode_bnc_in_state_led,
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/*******************************************************************************
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* TIMECODE_OUTPUT *
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*******************************************************************************/
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output timecode_out_bnc,
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output timecode_out_bnc_select,
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output timecode_out_bnc_state_led,
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output timecode_out_headphone,
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output timecode_out_headphone_select,
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output timecode_out_headphone_state_led,
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/*******************************************************************************
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* STM32_IF *
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*******************************************************************************/
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output stm32if_start_signal_out,
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output stm32if_camera_sync_out,
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output stm32if_timecode_sync_out,
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//SPI 串行总线1
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input wire spi1_cs_pin,
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input wire spi1_clk_pin,
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input wire spi1_rx_pin,
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output wire spi1_tx_pin,
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//SPI 串行总线2
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input wire spi2_cs_pin,
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input wire spi2_clk_pin,
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input wire spi2_rx_pin,
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output wire spi2_tx_pin,
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/*******************************************************************************
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* debug_signal_output *
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*******************************************************************************/
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output [15:0] debug_signal_output,
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/*******************************************************************************
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* CODE_BOARD *
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*******************************************************************************/
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output wire core_board_debug_led
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);
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localparam HARDWARE_TEST_MODE = 1;
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//STM32寄存器地址
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localparam REG_ADD_OFF_STM32 = 16'h0000;
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localparam REG_ADD_OFF_FPGA_TEST = 16'h00020;
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//控制中心寄存器地址
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localparam REG_ADD_OFF_XSYNC_INTERNAL_SIG_GENERATOR = 16'h00030; // 48
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//输入组件
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localparam REG_ADD_OFF_TTLIN1 = 16'h0100;
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localparam REG_ADD_OFF_TTLIN2 = 16'h0110;
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localparam REG_ADD_OFF_TTLIN3 = 16'h0120;
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localparam REG_ADD_OFF_TTLIN4 = 16'h0130;
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localparam REG_ADD_OFF_TIMECODE_IN = 16'h0140;
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localparam REG_ADD_OFF_GENLOCK_IN = 16'h0150;
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//输出组件
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localparam REG_ADD_OFF_TTLOUT1 = 16'h0200;
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localparam REG_ADD_OFF_TTLOUT2 = 16'h0210;
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localparam REG_ADD_OFF_TTLOUT3 = 16'h0220;
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localparam REG_ADD_OFF_TTLOUT4 = 16'h0230;
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localparam REG_ADD_OFF_TIMECODE_OUT = 16'h0240;
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localparam REG_ADD_OFF_GENLOCK_OUT = 16'h0250;
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localparam REG_ADD_OFF_CAMERA_SYNC_OUT = 16'h0260;
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//调试组件
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localparam REG_ADD_OFF_DEBUGER = 16'h0300;
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SPLL spll (
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.clkin1(ex_clk), // input
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.pll_lock(pll_lock), // output
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.clkout0(sys_clk_25m), // output
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.clkout1(sys_clk_10m), // output
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.clkout2(sys_clk_5m) // output
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);
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assign sys_clk = sys_clk_10m;
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assign sys_rst_n = ex_rst_n & pll_lock;
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localparam SYS_CLOCK_FREQ = 10000000;
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// zutils_reset_sig_gen reset_sig_gen_inst (
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// .clk(sys_clk),
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// .rst_n(rst_n),
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// .rst_n_out(sys_rst_n)
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// );
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/*******************************************************************************
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* DEBUG_LED *
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*******************************************************************************/
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// zutils_debug_led #(
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// .PERIOD_COUNT(10000000)
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// ) core_board_debug_led_inst (
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// .clk(sys_clk),
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// .rst_n(sys_rst_n),
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// .debug_led(core_board_debug_led)
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// );
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/*******************************************************************************
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* SPIREADER *
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*******************************************************************************/
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wire [31:0] reg_reader_bus_addr;
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wire [31:0] reg_reader_bus_wr_data;
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wire reg_reader_bus_wr_en;
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wire [31:0] reg_reader_bus_rd_data;
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spi_reg_reader spi_reg_reader_inst (
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.clk (sys_clk),
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.rst_n(sys_rst_n),
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.addr(reg_reader_bus_addr),
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.wr_data(reg_reader_bus_wr_data),
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.wr_en(reg_reader_bus_wr_en),
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.rd_data(reg_reader_bus_rd_data),
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//
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.spi_cs_pin(spi2_cs_pin),
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.spi_clk_pin(spi2_clk_pin),
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.spi_rx_pin(spi2_rx_pin),
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.spi_tx_pin(spi2_tx_pin)
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);
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wire [31:0] stm32_rd_data; //
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wire [31:0] fpga_test_rd_data; //
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wire [31:0] xsync_internal_sig_generator_rd_data;
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wire [31:0] ttlin1_rd_data;
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wire [31:0] ttlin2_rd_data;
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wire [31:0] ttlin3_rd_data;
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wire [31:0] ttlin4_rd_data;
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wire [31:0] timecode_in_rd_data;
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wire [31:0] genlock_in_rd_data;
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wire [31:0] ttlout1_rd_data;
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wire [31:0] ttlout2_rd_data;
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wire [31:0] ttlout3_rd_data;
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wire [31:0] ttlout4_rd_data;
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wire [31:0] timecode_out_rd_data;
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wire [31:0] genlock_out_rd_data;
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wire [31:0] camera_sync_out_rd_data;
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wire [31:0] debuger_rd_data;
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//
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/*******************************************************************************
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* TEST_SPI_REG *
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*******************************************************************************/
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zutils_register16 #(
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.REG_START_ADD(REG_ADD_OFF_FPGA_TEST),
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.REG0_INIT(31'h0000_0000_0000_0001),
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.REG1_INIT(31'h0000_0000_0000_0010),
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.REG2_INIT(31'h0000_0000_0000_0100),
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.REG3_INIT(31'h0000_0000_0000_1000),
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.REG4_INIT(31'h0000_0000_0001_0000),
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.REG5_INIT(31'h0000_0000_0010_0000),
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.REG6_INIT(31'h0000_0000_0100_0000),
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.REG7_INIT(31'h0000_0000_1000_0000),
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.REG8_INIT(31'h0000_0001_0000_0000),
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.REG9_INIT(31'h0000_0010_0000_0000),
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.REGA_INIT(31'h0000_0100_0000_0000),
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.REGB_INIT(31'h0000_1000_0000_0000),
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.REGC_INIT(31'h0001_0000_0000_0000),
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.REGD_INIT(31'h0010_0000_0000_0000),
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.REGE_INIT(31'h0100_0000_0000_0000),
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.REGF_INIT(31'h1000_0000_0000_0000)
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) test_reg (
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.clk(sys_clk),
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.rst_n(sys_rst_n),
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.addr(reg_reader_bus_addr),
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.wr_data(reg_reader_bus_wr_data),
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.wr_en(reg_reader_bus_wr_en),
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.rd_data(fpga_test_rd_data)
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);
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/*******************************************************************************
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* 信号源 *
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*******************************************************************************/
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wire ISIG_logic0; // 逻辑0
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wire ISIG_logic1; // 逻辑1
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wire ISIG_ttlin1_module_ext; // ttl1输入模块原始信号
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wire ISIG_ttlin1_module_divide; // ttl1输入模块分频信号
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wire ISIG_ttlin2_module_ext; // ttl2输入模块原始信号
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wire ISIG_ttlin2_module_divide; // ttl2输入模块分频信号
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wire ISIG_ttlin3_module_ext; // ttl3输入模块原始信号
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wire ISIG_ttlin3_module_divide; // ttl3输入模块分频信号
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wire ISIG_ttlin4_module_ext; // ttl4输入模块原始信号
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wire ISIG_ttlin4_module_divide; // ttl4输入模块分频信号
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wire ISIG_internal_en_flag; // 内部使能状态信号输出
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wire ISIG_genlock_frame_sync_ext; // 外部genlock帧同步信号
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wire ISIG_genlock_frame_sync_internal; // 内部genlock帧同步信号
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wire ISIG_timecode_frame_sync_ext; // 外部timecode帧同步信号
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wire ISIG_timecode_frame_sync_internal; // 内部timecode帧同步信号
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wire ISIG_timecode_serial_data_ext; // 外部timecode串行数据输入
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wire ISIG_timecode_serial_data_internal; // 内部timecode串行数据输入
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wire ISIG_internal_100hz; // 100hz测试信号
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wire [63:0] ISIGBUS64_timecode_data_ext;
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wire [31:0] ISIGBUS32_timecode_format_ext;
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wire [63:0] ISIGBUS64_timecode_data_internal;
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wire [31:0] ISIGBUS32_timecode_format_internal;
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assign ISIG_genlock_frame_sync_ext = genlock_in_vsync;
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assign ISIG_logic0 = 0;
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assign ISIG_logic1 = 1;
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/*******************************************************************************
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* TTL输出模块信号源分配 *
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*******************************************************************************/
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wire [31:0] ttl_output_module_source_sig_af;
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assign ttl_output_module_source_sig_af[0] = ISIG_logic0;
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assign ttl_output_module_source_sig_af[1] = ISIG_logic1;
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assign ttl_output_module_source_sig_af[2] = ISIG_ttlin1_module_ext;
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assign ttl_output_module_source_sig_af[3] = ISIG_ttlin1_module_divide;
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assign ttl_output_module_source_sig_af[4] = ISIG_ttlin2_module_ext;
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assign ttl_output_module_source_sig_af[5] = ISIG_ttlin2_module_divide;
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assign ttl_output_module_source_sig_af[6] = ISIG_ttlin3_module_ext;
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assign ttl_output_module_source_sig_af[7] = ISIG_ttlin3_module_divide;
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assign ttl_output_module_source_sig_af[8] = ISIG_ttlin4_module_ext;
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assign ttl_output_module_source_sig_af[9] = ISIG_ttlin4_module_divide;
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assign ttl_output_module_source_sig_af[10] = ISIG_internal_en_flag;
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assign ttl_output_module_source_sig_af[11] = ISIG_genlock_frame_sync_ext;
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assign ttl_output_module_source_sig_af[12] = ISIG_genlock_frame_sync_internal;
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assign ttl_output_module_source_sig_af[13] = ISIG_timecode_frame_sync_ext;
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assign ttl_output_module_source_sig_af[14] = ISIG_timecode_frame_sync_internal;
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assign ttl_output_module_source_sig_af[15] = ISIG_timecode_serial_data_ext;
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assign ttl_output_module_source_sig_af[16] = ISIG_timecode_serial_data_internal;
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assign ttl_output_module_source_sig_af[31] = ISIG_internal_100hz;
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xsync_internal_generator #(
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.REG_START_ADD (REG_ADD_OFF_XSYNC_INTERNAL_SIG_GENERATOR),
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.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ)
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) xsync_internal_generator_ins (
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.clk(sys_clk),
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.rst_n(sys_rst_n),
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.addr(reg_reader_bus_addr),
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.wr_data(reg_reader_bus_wr_data),
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.wr_en(reg_reader_bus_wr_en),
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.rd_data(xsync_internal_sig_generator_rd_data),
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.ext_ttlin1_module_raw_sig(ISIG_ttlin1_module_ext),
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.ext_ttlin2_module_raw_sig(ISIG_ttlin2_module_ext),
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.ext_ttlin3_module_raw_sig(ISIG_ttlin3_module_ext),
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.ext_ttlin4_module_raw_sig(ISIG_ttlin4_module_ext),
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.ext_timecode_tigger_sig(ISIG_timecode_frame_sync_ext),
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.ext_timecode_data(ISIGBUS64_timecode_data_ext),
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.ext_genlock_signal(ISIG_genlock_frame_sync_ext),
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.out_timecode_tirgger_sig(ISIG_timecode_frame_sync_internal), //输出时码译码有效信号
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.out_timecode_sig(ISIGBUS64_timecode_data_internal), //[63:0] 输出时间
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.out_timecode_serial_sig(ISIG_timecode_serial_data_internal), //TIMECODE串行数据输出
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.out_genlock_sig(ISIG_genlock_frame_sync_internal),
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.out_en_flag(ISIG_internal_en_flag)
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);
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/*******************************************************************************
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* 时码解析器 *
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*******************************************************************************/
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timecode_input_parser #(
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.REG_START_ADD (REG_ADD_OFF_TIMECODE_IN),
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.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ)
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) timecode_input_parser_ins (
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.clk (sys_clk),
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.rst_n(sys_rst_n),
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.addr(reg_reader_bus_addr),
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.wr_data(reg_reader_bus_wr_data),
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.wr_en(reg_reader_bus_wr_en),
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.rd_data(timecode_in_rd_data),
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//input
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.timecode_bnc_in(timecode_bnc_in),
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.timecode_headphone_in(timecode_headphone_in),
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//output
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.timecode_tigger_sig(ISIG_timecode_frame_sync_ext),
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.timecode_format(ISIGBUS32_timecode_format_ext), //[31:0]
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.timecode_data(ISIGBUS64_timecode_data_ext), //[63:0]
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.timecode_serial_data(ISIG_timecode_serial_data_ext),
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.timecode_headphone_in_state_led(timecode_headphone_in_state_led),
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.timecode_bnc_in_state_led(timecode_bnc_in_state_led)
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);
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/*******************************************************************************
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* ISIG_internal_100hz信号生成 *
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*******************************************************************************/
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zutils_pwm_generator #(
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.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ),
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.OUTPUT_FREQ(100)
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) pwm100hz_gen (
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.clk(sys_clk),
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.rst_n(sys_rst_n),
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.output_signal(ISIG_internal_100hz)
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);
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// ===========================================================================================================
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// 输出组件
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// ===========================================================================================================
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//
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camera_sync_signal_output #(
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.REG_START_ADD (REG_ADD_OFF_CAMERA_SYNC_OUT),
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.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ)
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) camera_sync_signal_output_ist (
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.clk (sys_clk),
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.rst_n(sys_rst_n),
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.addr(reg_reader_bus_addr),
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.wr_data(reg_reader_bus_wr_data),
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.wr_en(reg_reader_bus_wr_en),
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.rd_data(camera_sync_out_rd_data),
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.internal_genlock_sig(ISIG_genlock_frame_sync_internal),
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.ext_genlock_sig(ISIG_genlock_frame_sync_ext),
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.test_100hz_sig(ISIG_internal_100hz),
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.stm32if_camera_sync_out(stm32if_camera_sync_out)
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);
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/*******************************************************************************
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* STM32_IF *
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*******************************************************************************/
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assign stm32if_start_signal_out = ISIG_internal_en_flag;
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/*******************************************************************************
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* timecode_output *
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*******************************************************************************/
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timecode_output #(
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.REG_START_ADD (REG_ADD_OFF_TIMECODE_OUT),
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.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ)
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) timecode_output_inst (
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.clk (sys_clk),
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.rst_n(sys_rst_n),
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.addr(reg_reader_bus_addr),
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.wr_data(reg_reader_bus_wr_data),
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.wr_en(reg_reader_bus_wr_en),
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.rd_data(timecode_out_rd_data),
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.ext_timecode_data(ISIGBUS64_timecode_data_ext), //63:0
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.ext_timecode_format(ISIGBUS32_timecode_format_ext), //31:0
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.ext_timecode_tigger_sig(ISIG_timecode_frame_sync_ext),
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.ext_timecode_serial_data(ISIG_timecode_serial_data_ext),
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.internal_timecode_data(ISIGBUS64_timecode_data_internal), //63:0
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.internal_timecode_format(ISIGBUS32_timecode_format_internal), //31:0
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.internal_timecode_tigger_sig(ISIG_timecode_frame_sync_internal),
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.internal_timecode_serial_data(ISIG_timecode_serial_data_internal),
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.stm32if_timecode_tigger_sig(stm32if_timecode_sync_out),
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.timecode_out_bnc(timecode_out_bnc),
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.timecode_out_bnc_select(timecode_out_bnc_select),
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.timecode_out_bnc_state_led(timecode_out_bnc_state_led),
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.timecode_out_headphone(timecode_out_headphone),
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.timecode_out_headphone_select(timecode_out_headphone_select),
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.timecode_out_headphone_state_led(timecode_out_headphone_state_led)
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);
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/*******************************************************************************
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* TTL_OUTPUT *
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*******************************************************************************/
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ttl_output #(
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.REG_START_ADD(REG_ADD_OFF_TTLOUT1),
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.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ),
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.ID(1)
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) ttl_output_1 (
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.clk (sys_clk),
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.rst_n(sys_rst_n),
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.addr(reg_reader_bus_addr),
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.wr_data(reg_reader_bus_wr_data),
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.wr_en(reg_reader_bus_wr_en),
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.rd_data(ttlout1_rd_data),
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.signal_in(ttl_output_module_source_sig_af),
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.ttloutput(sync_ttl_out1),
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.ttloutput_state_led(sync_ttl_out1_state_led)
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);
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ttl_output #(
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.REG_START_ADD(REG_ADD_OFF_TTLOUT2),
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.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ),
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.ID(2)
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) ttl_output_2 (
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.clk (sys_clk),
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.rst_n(sys_rst_n),
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.addr(reg_reader_bus_addr),
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.wr_data(reg_reader_bus_wr_data),
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.wr_en(reg_reader_bus_wr_en),
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.rd_data(ttlout2_rd_data),
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.signal_in(ttl_output_module_source_sig_af),
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.ttloutput(sync_ttl_out2),
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.ttloutput_state_led(sync_ttl_out2_state_led)
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);
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ttl_output #(
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.REG_START_ADD(REG_ADD_OFF_TTLOUT3),
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.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ),
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.ID(3)
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) ttl_output_3 (
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.clk (sys_clk),
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.rst_n(sys_rst_n),
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.addr(reg_reader_bus_addr),
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.wr_data(reg_reader_bus_wr_data),
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.wr_en(reg_reader_bus_wr_en),
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.rd_data(ttlout3_rd_data),
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.signal_in(ttl_output_module_source_sig_af),
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.ttloutput(sync_ttl_out3),
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.ttloutput_state_led(sync_ttl_out3_state_led)
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);
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ttl_output #(
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.REG_START_ADD(REG_ADD_OFF_TTLOUT4),
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.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ),
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.ID(4)
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) ttl_output_4 (
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.clk (sys_clk),
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.rst_n(sys_rst_n),
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.addr(reg_reader_bus_addr),
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.wr_data(reg_reader_bus_wr_data),
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.wr_en(reg_reader_bus_wr_en),
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.rd_data(ttlout4_rd_data),
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.signal_in(ttl_output_module_source_sig_af),
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.ttloutput(sync_ttl_out4),
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.ttloutput_state_led(sync_ttl_out4_state_led)
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);
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rd_data_router #(
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.REG_ADD_OFF_STM32(REG_ADD_OFF_STM32),
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.REG_ADD_OFF_FPGA_TEST(REG_ADD_OFF_FPGA_TEST),
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.REG_ADD_OFF_XSYNC_INTERNAL_SIG_GENERATOR(REG_ADD_OFF_XSYNC_INTERNAL_SIG_GENERATOR),
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.REG_ADD_OFF_TTLIN1(REG_ADD_OFF_TTLIN1),
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.REG_ADD_OFF_TTLIN2(REG_ADD_OFF_TTLIN2),
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.REG_ADD_OFF_TTLIN3(REG_ADD_OFF_TTLIN3),
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.REG_ADD_OFF_TTLIN4(REG_ADD_OFF_TTLIN4),
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.REG_ADD_OFF_TIMECODE_IN(REG_ADD_OFF_TIMECODE_IN),
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.REG_ADD_OFF_GENLOCK_IN(REG_ADD_OFF_GENLOCK_IN),
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.REG_ADD_OFF_TTLOUT1(REG_ADD_OFF_TTLOUT1),
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.REG_ADD_OFF_TTLOUT2(REG_ADD_OFF_TTLOUT2),
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.REG_ADD_OFF_TTLOUT3(REG_ADD_OFF_TTLOUT3),
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.REG_ADD_OFF_TTLOUT4(REG_ADD_OFF_TTLOUT4),
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.REG_ADD_OFF_TIMECODE_OUT(REG_ADD_OFF_TIMECODE_OUT),
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.REG_ADD_OFF_GENLOCK_OUT(REG_ADD_OFF_GENLOCK_OUT),
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.REG_ADD_OFF_CAMERA_SYNC_OUT(REG_ADD_OFF_CAMERA_SYNC_OUT),
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.REG_ADD_OFF_DEBUGER(REG_ADD_OFF_DEBUGER)
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) rd_data_router_inst (
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.addr(reg_reader_bus_addr),
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.stm32_rd_data(stm32_rd_data),
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.fpga_test_rd_data(fpga_test_rd_data),
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.xsync_internal_sig_generator_rd_data(xsync_internal_sig_generator_rd_data),
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.ttlin1_rd_data(ttlin1_rd_data),
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.ttlin2_rd_data(ttlin2_rd_data),
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.ttlin3_rd_data(ttlin3_rd_data),
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.ttlin4_rd_data(ttlin4_rd_data),
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.timecode_in_rd_data(timecode_in_rd_data),
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.genlock_in_rd_data(genlock_in_rd_data),
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.ttlout1_rd_data(ttlout1_rd_data), // ok
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.ttlout2_rd_data(ttlout2_rd_data), // ok
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.ttlout3_rd_data(ttlout3_rd_data), // ok
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.ttlout4_rd_data(ttlout4_rd_data), // ok
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.timecode_out_rd_data(timecode_out_rd_data),
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.genlock_out_rd_data(genlock_out_rd_data),
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.camera_sync_out_rd_data(camera_sync_out_rd_data),
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.debuger_rd_data(debuger_rd_data),
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.rd_data_out(reg_reader_bus_rd_data)
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);
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// assign reg_reader_bus_rd_data[31:0] = fpga_test_rd_data[31:0];
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// output reg stm32if_timecode_tigger_sig,
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// output reg timecode_out_bnc,
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// output reg timecode_out_bnc_select, // 电平选择 0line,1:mic
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// output reg timecode_out_bnc_state_led,
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// output reg timecode_out_headphone,
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// output reg timecode_out_headphone_select, // 电平选择 0line,1:mic
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// output reg timecode_out_headphone_state_led
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assign debug_signal_output[0] = sync_ttl_out1;
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assign debug_signal_output[1] = sync_ttl_out2;
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assign debug_signal_output[2] = sync_ttl_out3;
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assign debug_signal_output[3] = sync_ttl_out4;
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assign debug_signal_output[4] = stm32if_timecode_sync_out;
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assign debug_signal_output[5] = timecode_out_bnc;
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assign debug_signal_output[6] = timecode_out_headphone;
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assign debug_signal_output[7] = genlock_in_hsync;
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assign debug_signal_output[8] = genlock_in_vsync;
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assign debug_signal_output[9] = genlock_in_fsync;
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assign debug_signal_output[10] = sync_ttl_in1;
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assign debug_signal_output[11] = sync_ttl_in2;
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assign debug_signal_output[12] = sync_ttl_in3;
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assign debug_signal_output[13] = sync_ttl_in4;
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assign debug_signal_output[14] = timecode_headphone_in;
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assign debug_signal_output[15] = timecode_bnc_in;
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assign core_board_debug_led = 1;
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assign genlock_in_state_led = 1;
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endmodule
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