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18 lines
364 B
18 lines
364 B
/*
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* Hacky baud rate generator to divide a 50MHz clock into a 115200 baud
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* rx/tx pair where the rx clcken oversamples by 16x.
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*/
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module monitor_line (
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input wire clk_50m,
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input wire rst_n,
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input wire in,
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output reg out
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);
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always @(posedge clk_50m or negedge rst_n) begin
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if (!rst_n) out <= 1'b0;
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else out <= in;
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end
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endmodule
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