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32 lines
730 B
32 lines
730 B
`timescale 1ns / 1ns
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module Top (
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input sys_clk,
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input rst_n,
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output reg [3:0] led,
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output reg [3:0] key,
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output wire usb_serial_tx,
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input wire usb_serial_rx,
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output wire [35:3] test_io
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);
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wire inclkpll_clk0out;
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inclkpll inclkpll_inst (
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.clkin1 (sys_clk),
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.clkout0(inclkpll_clk0out)
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);
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uart_reg_reader uart_reg_reader_impl (
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.clk(sys_clk),
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.rst_n(rst_n),
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.reg_data(),
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.reg_add(),
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.reg_add_valid(),
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.uart_rx_pin(usb_serial_rx),
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.uart_tx_pin(usb_serial_tx)
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);
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monitor_line monitor_line_usb_serial_rx(sys_clk, rst_n, usb_serial_rx, test_io[4]);
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assign test_io[3] = usb_serial_tx;
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// assign test_io[3] = inclkpll_clk0out;
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endmodule
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