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41 lines
675 B
41 lines
675 B
`timescale 1ns / 1ns
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module Top (
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input sys_clk,
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input rst_n,
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output wire core_board_debug_led
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);
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zutils_debug_led #(
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.PERIOD_COUNT(10000000)
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) core_board_debug_led_inst (
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.clk(sys_clk),
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.rst_n(rst_n),
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.debug_led(core_board_debug_led)
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);
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//
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//
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//
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//
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// wire inclkpll_clk0out;
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// inclkpll inclkpll_inst (
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// .clkin1 (sys_clk),
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// .clkout0(inclkpll_clk0out)
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// );
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// des_ttl_generator des_ttl_generator_inst (
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// .clk(sys_clk),
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// .rst_n(rst_n),
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// .addr(),
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// .wr_data(0),
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// .wr_en(0),
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// .rd_data(),
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// .signal_in(1),
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// .ttloutput(test_io[3])
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// );
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endmodule
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