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27 lines
402 B
27 lines
402 B
`timescale 10ns / 10ns
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module test_top;
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reg sys_clk;
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reg rst_n;
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wire core_board_debug_led;
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Top top_impl (
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.sys_clk(sys_clk),
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.rst_n(rst_n),
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.core_board_debug_led(core_board_debug_led)
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);
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initial begin
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sys_clk = 0;
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rst_n = 0;
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#100;
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rst_n = 1;
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#15;
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// #5000000;
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// $stop;
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end
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always #1 sys_clk = ~sys_clk; // 50MHZ时钟
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endmodule
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