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109 lines
2.3 KiB
109 lines
2.3 KiB
`timescale 10ns / 10ns
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module test_top;
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reg sys_clk;
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reg rst_n;
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wire core_board_debug_led;
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reg spi2_cs_pin;
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reg spi2_clk_pin;
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reg spi2_tx_pin;
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wire spi2_rx_pin;
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wire sync_ttl_out1;
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wire sync_ttl_out1_state_led;
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wire sync_ttl_out2;
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wire sync_ttl_out2_state_led;
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wire sync_ttl_out3;
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wire sync_ttl_out3_state_led;
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wire sync_ttl_out4;
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wire sync_ttl_out4_state_led;
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initial begin
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spi2_cs_pin = 1;
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spi2_clk_pin = 1;
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spi2_tx_pin = 1;
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end
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task spi_write_reg;
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input [15:0] addr;
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input [31:0] data;
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integer i;
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begin
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addr[15] = 1;
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spi2_cs_pin = 0;
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#3000; // 100ns
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for (i = 0; i < 48; i = i + 1) begin
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spi2_clk_pin = 0;
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if (i <= 15) spi2_tx_pin = addr[i];
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else spi2_tx_pin = data[i-16];
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#300;
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spi2_clk_pin = 1;
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#300;
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end
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spi2_clk_pin = 0;
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#300;
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spi2_clk_pin = 1;
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#200;
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spi2_cs_pin = 1;
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spi2_tx_pin = 1;
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#3000;
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end
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endtask
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Top top_impl (
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.ex_clk(sys_clk),
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.ex_rst_n(rst_n),
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.core_board_debug_led(core_board_debug_led),
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.spi2_cs_pin (spi2_cs_pin),
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.spi2_clk_pin(spi2_clk_pin),
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.spi2_rx_pin (spi2_tx_pin),
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.spi2_tx_pin (spi2_rx_pin),
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.sync_ttl_out1(sync_ttl_out1),
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.sync_ttl_out1_state_led(sync_ttl_out1_state_led),
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.sync_ttl_out2(sync_ttl_out2),
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.sync_ttl_out2_state_led(sync_ttl_out2_state_led),
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.sync_ttl_out3(sync_ttl_out3),
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.sync_ttl_out3_state_led(sync_ttl_out3_state_led),
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.sync_ttl_out4(sync_ttl_out4),
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.sync_ttl_out4_state_led(sync_ttl_out4_state_led)
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);
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initial begin
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sys_clk = 0;
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rst_n = 0;
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#100;
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rst_n = 1;
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#1000;
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spi_write_reg(16'h0020, 32'h00000001);
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spi_write_reg(16'h0021, 32'h00000010);
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spi_write_reg(16'h0022, 32'h00000100);
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spi_write_reg(16'h0023, 32'h00001000);
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spi_write_reg(16'h0020, 32'h00000002);
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spi_write_reg(16'h0021, 32'h00000020);
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spi_write_reg(16'h0022, 32'h00000200);
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spi_write_reg(16'h0023, 32'h00002000);
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spi_write_reg(16'h00030+6, 32'h12345678); // 写SignalGenerator——TIMECODE0
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spi_write_reg(16'h00030+7, 32'h87654321); // 写SignalGenerator——TIMECODE0
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#100000000;
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$stop;
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end
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always #5 sys_clk = ~sys_clk; // 50MHZ时钟
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endmodule
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