fpga_led_test/source/src/xsync_internal_generator.v

// SIGNAL_GENERATOR
//      启动方式:
//           1.寄存器控制启动
//           2.外部触发启动
//           3.TIMECODE触发启动
//      帧格式:
//           TIMECODE:
//                25/30/...
//           GENLOCK:
//                ....
//      产生:
//           1.start_state_sig (高电平表示拍照进行中)
//           2.timecode_sig[64]
//           3.timecode_tirgger_sig[1]
//           4.genlock_sig[1] 帧信号,场信号
//

// TIMECODE_FORMAT
//      FPS2398Format = 0,
//      FPS2400Format = 1,
//      FPS2500Format = 2,
//      FPS2997Format = 3,
//      FPS2997DropFormat = 4,
//      FPS3000Format = 5

// GENLCOK_FORMAT
//      GENLOCK_FPS2397_FORMAT = 0
//      GENLOCK_FPS2398_FORMAT = 1
//      GENLOCK_FPS2400_FORMAT = 2
//      GENLOCK_FPS2500_FORMAT = 3
//      GENLOCK_FPS2997_FORMAT = 4
//      GENLOCK_FPS3000_FORMAT = 5
//      GENLOCK_FPS5000_FORMAT = 6
//      GENLOCK_FPS5994_FORMAT = 7
//      GENLOCK_FPS6000_FORMAT = 8



module xsync_internal_generator #(
    parameter REG_START_ADD = 0,
    parameter SYS_CLOCK_FREQ = 10000000,
    parameter TEST = 0,
    parameter ID = 1
) (
    input clk,   //clock input
    input rst_n, //asynchronous reset input, low active

    //寄存器读写接口    
    input       [31:0] addr,
    input       [31:0] wr_data,
    input              wr_en,
    output wire [31:0] rd_data,

    input wire ext_ttlin1_module_raw_sig,
    input wire ext_ttlin2_module_raw_sig,
    input wire ext_ttlin3_module_raw_sig,
    input wire ext_ttlin4_module_raw_sig,

    input wire ext_timecode_tigger_sig,
    input wire [63:0] ext_timecode_data,
    input wire ext_genlock_signal,  // 

    /*******************************************************************************
     *                              内部时码信号输出                               *
     *******************************************************************************/
    output wire out_timecode_tirgger_sig,  //输出时码译码有效信号
    output wire [63:0] out_timecode_sig,  // 输出时间
    output wire out_timecode_serial_sig,

    /*******************************************************************************
     *                             内部GENLOCK信号输出                             *
     *******************************************************************************/
    output wire out_genlock_sig,
    /*******************************************************************************
     *                            内部工作状态信号输出                             *
     *******************************************************************************/
    output wire out_en_flag

);

  localparam CTRL_REG_INDEX = 4;


  reg  [31:0] r0_start_control_mode_reg;  //控制模式选择寄存器
  reg  [31:0] r2_genlock_format;  //genlock格式寄存器
  reg  [31:0] r3_timecode_format;  //timecode格式寄存器
  reg  [31:0] r4_control_trigger_reg;  // StartSigCtrl[0] TimecodeCtrl[1] GenlockCtrl[2]
  wire [31:0] r6_timecode0;  //timecode0 belong to timecode_generator_ist
  wire [31:0] r7_timecode1;  //timecode1 belong to timecode_generator_ist
  reg  [31:0] r8_timecode_start0;  // 时码启动寄存器0
  reg  [31:0] r9_timecode_start1;  // 时码启动寄存器1
  reg  [31:0] rA_timecode_stop0;  // 时码停止寄存器0
  reg  [31:0] rB_timecode_stop1;  // 时码停止寄存器1
  reg  [31:0] rC_work_state;  //工作状态 read only
  assign out_en_flag = rC_work_state[0];

  //写寄存器标志位
  wire [31:0] reg_wr_index;

  zutils_register_advanced #(
      .REG_START_ADD(REG_START_ADD)
  ) _register (
      .clk(clk),
      .rst_n(rst_n),
      .addr(addr),
      .wr_data(wr_data),
      .wr_en(wr_en),
      .rd_data(rd_data),

      .reg0(r0_start_control_mode_reg),
      .reg2(r2_genlock_format),
      .reg3(r3_timecode_format),
      .reg4(r4_control_trigger_reg),
      .reg6(r6_timecode0),
      .reg7(r7_timecode1),
      .reg8(r8_timecode_start0),
      .reg9(r9_timecode_start1),
      .regA(rA_timecode_stop0),
      .regB(rB_timecode_stop1),
      .regC(rC_work_state),

      .reg_wr_sig(reg_wr_sig),
      .reg_index (reg_wr_index)
  );

  always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
      r0_start_control_mode_reg <= 0;
      r2_genlock_format <= 0;
      r3_timecode_format <= 0;
      r4_control_trigger_reg <= 0;
      r8_timecode_start0 <= 0;
      r9_timecode_start1 <= 0;
      rA_timecode_stop0 <= 0;
      rB_timecode_stop1 <= 0;
      // rC_work_state <= 0;
    end else begin
      if (reg_wr_sig) begin
        case (reg_wr_index)
          31'h0: r0_start_control_mode_reg <= wr_data;
          31'h2: r2_genlock_format <= wr_data;
          31'h3: r3_timecode_format <= wr_data;
          31'h4: r4_control_trigger_reg <= wr_data;
          31'h8: r8_timecode_start0 <= wr_data;
          31'h9: r9_timecode_start1 <= wr_data;
          31'hA: rA_timecode_stop0 <= wr_data;
          31'hB: rB_timecode_stop1 <= wr_data;
          // 31'hC: rC_work_state <= wr_data;
          default: begin
          end
        endcase
      end
    end
  end
  /*******************************************************************************
   *                                StartSig输出                                 *
   *******************************************************************************/

  //  1.寄存器控制启动
  //  2.外部触发启动
  //  3.TIMECODE触发启动

  //      0.寄存器触发,启动停止
  //      1.外部TIMECODE触发启动,寄存器控制停止
  //      2.外部TTL输入1_高电平触发,低电平停止
  //      3.外部TTL输入2_高电平触发,低电平停止
  //      4.外部TTL输入3_高电平触发,低电平停止
  //      5.外部TTL输入4_高电平触发,低电平停止
  //


  zutils_multiplexer_32t1_v2 ttlin_level_trigger_multi (
      .chooseindex(r0_start_control_mode_reg),
      //in
      .in2(ext_ttlin1_module_raw_sig),
      .in3(ext_ttlin2_module_raw_sig),
      .in4(ext_ttlin3_module_raw_sig),
      .in5(ext_ttlin4_module_raw_sig),
      //out
      .out(ext_ttlinx_module_raw_sig)
  );

  reg start_sig;
  always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
      start_sig <= 0;
      rC_work_state <= 0;
    end else begin
      case (r0_start_control_mode_reg[31:0])
        0: begin
          //寄存器控制启动

          if (reg_wr_sig && reg_wr_index == CTRL_REG_INDEX) begin
            if (wr_data[0] == 1) begin
              rC_work_state[0] <= 1;
            end else begin
              rC_work_state[0] <= 0;
            end
          end

        end
        1: begin
          //TIMECODE触发

        end
        2, 3, 4, 5: begin
          //外部电平控制
          if (ext_ttlinx_module_raw_sig == 1) begin
            rC_work_state[0] <= 1;
          end else begin
            rC_work_state[0] <= 0;
          end
        end
        default: begin
        end
      endcase
    end
  end


  /*******************************************************************************
   *                              GENLOCK_时钟输出                               *
   *******************************************************************************/

  wire genlock_sig_output;
  zutils_genlock_clk_generator #(
      .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ)
  ) genlock (
      .clk(clk),
      .rst_n(rst_n),
      .ctrl_sig(out_en_flag),
      .genlock_fps2397_clk(genlock_fps2397_clk),
      .genlock_fps2398_clk(genlock_fps2398_clk),
      .genlock_fps2400_clk(genlock_fps2400_clk),
      .genlock_fps2500_clk(genlock_fps2500_clk),
      .genlock_fps2997_clk(genlock_fps2997_clk),
      .genlock_fps3000_clk(genlock_fps3000_clk),
      .genlock_fps5000_clk(genlock_fps5000_clk),
      .genlock_fps5994_clk(genlock_fps5994_clk),
      .genlock_fps6000_clk(genlock_fps6000_clk)
  );

  zutils_multiplexer_32t1_v2 genlock_clk_output_mult (
      .chooseindex(genlock_format),
      //in
      .in0(genlock_fps2397_clk),
      .in1(genlock_fps2398_clk),
      .in2(genlock_fps2400_clk),
      .in3(genlock_fps2500_clk),
      .in4(genlock_fps2997_clk),
      .in5(genlock_fps3000_clk),
      .in6(genlock_fps5000_clk),
      .in7(genlock_fps5994_clk),
      .in8(genlock_fps6000_clk),
      //out
      .out(genlock_sig_output)
  );
  assign out_genlock_sig = genlock_sig_output;

  /*******************************************************************************
   *                        smpte_timecode_clk_generator                         *
   *******************************************************************************/

  timecode_generator #(
      .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ)
  ) timecode_generator_ist (
      .clk  (clk),
      .rst_n(rst_n),

      .timecode_format(r3_timecode_format),

      .timecode0_wen(addr == 6),
      .timecode0(wr_data),
      .timecode1_wen(addr == 7),
      .timecode1(wr_data),

      .timecode0_export(r6_timecode0),
      .timecode1_export(r7_timecode1),

      .en(out_en_flag),

      .out_timecode_serial_data(out_timecode_serial_sig),
      .out_trigger_sig(out_timecode_tirgger_sig),
      .out_timecode0(out_timecode_sig[31:0]),
      .out_timecode1(out_timecode_sig[63:32])
  );


endmodule