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58 lines
1.8 KiB
58 lines
1.8 KiB
#Generated by Fabric Compiler ( version 2021.1-SP7 <build 86875> ) at Fri Dec 8 16:54:29 2023
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add_design "D:/workspace/fpga_demo/led_test/source/led_test.v"
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set_arch -family Logos -device PGL22G -speedgrade -6 -package MBG324
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compile -top_module led_test
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add_constraint "D:/workspace/fpga_demo/led_test/led_test.fdc"
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synthesize -ads -selected_syn_tool_opt 2
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dev_map
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pnr
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pnr
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pnr
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pnr
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pnr
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pnr
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synthesize -ads -selected_syn_tool_opt 2
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dev_map
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pnr
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report_timing
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gen_bit_stream
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synthesize -ads -selected_syn_tool_opt 2
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dev_map
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pnr
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report_timing
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gen_bit_stream
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add_design D:/workspace/fpga_demo/led_test/ipcore/clk_wiz_0/clk_wiz_0.idf
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add_design D:/workspace/fpga_demo/led_test/ipcore/ram/ram.idf
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remove_design -force D:/workspace/fpga_demo/led_test/ipcore/clk_wiz_0/clk_wiz_0.idf
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gen_bit_stream
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gen_bit_stream
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gen_bit_stream
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gen_bit_stream
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set_arch -family Logos -device PGL22G -speedgrade -6 -package MBG324
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compile -top_module led_test
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synthesize -ads -selected_syn_tool_opt 2
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dev_map
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pnr
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report_timing
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gen_bit_stream
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set_arch -family Logos -device PGL22G -speedgrade -6 -package MBG324
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compile -top_module led_test
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synthesize -ads -selected_syn_tool_opt 2
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dev_map
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pnr
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report_timing
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gen_bit_stream
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set_arch -family Logos -device PGL22G -speedgrade -6 -package MBG324
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compile -top_module led_test
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set_arch -family Logos -device PGL22G -speedgrade -6 -package MBG324
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compile -top_module led_test
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synthesize -ads -selected_syn_tool_opt 2
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dev_map
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pnr
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report_timing
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gen_bit_stream
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add_simulation "D:/workspace/fpga_demo/led_test/source/vtf_led.test.v"
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remove_simulation -force "D:/workspace/fpga_demo/led_test/source/vtf_led.test.v"
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add_simulation "D:/workspace/fpga_demo/led_test/source/test.v"
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add_design "D:/workspace/fpga_demo/led_test/source/source/async.v"
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