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44 lines
1.6 KiB
44 lines
1.6 KiB
`timescale 1ns/1ns
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module led_test
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(
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sys_clk, // system clock 50Mhz on board
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rst_n, // reset ,low active
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led // LED,use for control the LED signal on board
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);
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input sys_clk;
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input rst_n;
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output [3:0] led;
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//define the time counter
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reg [31:0] timer;
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reg [3:0] led;
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always @(posedge sys_clk or negedge rst_n)
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begin
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if (~rst_n)
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timer <= 32'd0; // when the reset signal valid,time counter clearing
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else if (timer == 32'd199_9999_9) //4 seconds count(50M*4-1=199999999)
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timer <= 32'd0; //count done,clearing the time counter
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else
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timer <= timer + 1'b1; //timer counter = timer counter + 1
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end
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always @(posedge sys_clk or negedge rst_n)
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begin
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if (~rst_n)
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led <= 4'b0000; //when the reset signal active
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else if (timer == 32'd49_999_9) //time counter count to 1st sec,LED1 Extinguish
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led <= 4'b0001;
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else if (timer == 32'd99_999_9) //time counter count to 2nd sec,LED2 Extinguish
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begin
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led <= 4'b0010;
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end
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else if (timer == 32'd149_999_9) //time counter count to 3nd sec,LED3 Extinguish
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led <= 4'b0100;
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else if (timer == 32'd199_999_9) //time counter count to 4nd sec,LED4 Extinguish
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led <= 4'b1000;
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end
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endmodule
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