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295 lines
10 KiB
295 lines
10 KiB
(_flow fab_demo "2021.1-SP7"
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(_comment "Generated by Fabric Compiler (version on 2021.1-SP7<build 86875>) at Sun Dec 31 15:14:14 2023")
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(_version "1.0.5")
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(_status "initial")
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(_project
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)
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(_task tsk_setup
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(_widget wgt_select_arch
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(_input
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(_part
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(_family Logos)
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(_device PGL22G)
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(_speedgrade -6)
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(_package MBG324)
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)
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)
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)
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(_widget wgt_my_design_src
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(_input
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(_file "source/src/transmitter.v"
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(_format verilog)
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(_timespec "2023-12-14T15:23:21")
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)
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(_file "source/src/baud_rate_gen.v"
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(_format verilog)
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(_timespec "2023-12-13T15:21:23")
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)
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(_file "source/src/top.v" + "Top:"
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(_format verilog)
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(_timespec "2023-12-31T15:13:50")
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)
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(_file "source/src/uart_tx.v"
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(_format verilog)
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(_timespec "2017-08-01T15:37:24")
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)
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(_file "source/src/uart_rx.v"
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(_format verilog)
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(_timespec "2023-12-13T10:31:56")
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)
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(_file "source/src/uart_reg_reader.v"
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(_format verilog)
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(_timespec "2023-12-15T09:32:26")
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)
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(_file "source/src/monitor_line.v"
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(_format verilog)
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(_timespec "2023-12-14T21:44:03")
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)
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(_file "source/src/spi_reg_reader.v"
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(_format verilog)
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(_timespec "2023-12-15T22:06:08")
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)
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(_file "source/src/src_ttl_parser.v"
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(_format verilog)
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(_timespec "2023-12-30T15:38:08")
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)
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(_file "source/src/src_timecode.v"
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(_format verilog)
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(_timespec "2023-12-30T20:50:11")
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)
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(_file "source/src/des_ttl_generator.v"
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(_format verilog)
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(_timespec "2023-12-31T15:12:53")
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)
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(_file "source/src/zutils/zutils_pluse_generator.v"
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(_format verilog)
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(_timespec "2023-12-31T14:50:20")
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)
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(_file "source/src/zutils/zutils_edge_detecter.v"
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(_format verilog)
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(_timespec "2023-12-31T15:00:01")
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)
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(_file "source/src/zutils/zutils_register.v"
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(_format verilog)
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(_timespec "2023-12-31T14:53:25")
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)
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)
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)
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(_widget wgt_my_ips_src
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(_input
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(_ip "ipcore/inclkpll/inclkpll.idf"
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(_timespec "2023-12-14T21:34:50")
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(_ip_source_item "ipcore/inclkpll/inclkpll.v"
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(_timespec "2023-12-14T21:34:50")
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)
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)
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(_ip "ipcore/ttl_pll/ttl_pll.idf"
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(_timespec "2023-12-30T15:00:33")
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)
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)
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)
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(_widget wgt_import_logic_con_file
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(_input
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(_file "led_test.fdc"
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(_format fdc)
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(_timespec "2023-12-14T21:55:40")
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)
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)
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)
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(_widget wgt_edit_user_cons
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(_attribute _click_to_run (_switch ON))
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)
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(_widget wgt_simulation
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(_option compiled_lib_location (_string "pango_sim_libraries"))
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(_option verilog_options (_string ""))
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(_option gen_param (_string ""))
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(_option simulate_runtime (_string "10000ms"))
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(_option sim_exe_dir (_string "C:/modeltech64_10.5/win64"))
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(_input
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(_file "source/test/test_transmitter.v"
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(_format verilog)
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(_timespec "2023-12-13T19:33:40")
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)
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(_file "source/test/test_baud_rate_gen.v"
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(_format verilog)
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(_timespec "2023-12-13T19:30:23")
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)
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(_file "source/test/test_top.v"
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(_format verilog)
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(_timespec "2023-12-13T21:56:53")
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)
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(_file "source/test/test_uart_reg_reader.v"
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(_format verilog)
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(_timespec "2023-12-15T22:18:26")
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)
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(_file "source/test/test_spi_reg_reader.v" + "test_spi_reg_reader:"
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(_format verilog)
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(_timespec "2023-12-15T22:10:16")
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)
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)
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)
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)
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(_task tsk_compile
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(_command cmd_compile
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(_gci_state (_integer 2))
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(_db_output
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(_file "compile/Top_comp.adf"
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(_format adif)
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(_timespec "2023-12-31T15:14:05")
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)
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)
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(_output
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(_file "compile/Top.cmr"
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(_format verilog)
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(_timespec "2023-12-31T15:14:04")
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)
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(_file "compile/cmr.db"
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(_format text)
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(_timespec "2023-12-31T15:14:05")
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)
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)
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)
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(_widget wgt_rtl_view
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(_attribute _click_to_run (_switch ON))
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)
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)
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(_task tsk_synthesis
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(_command cmd_synthesize
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(_gci_state (_integer 2))
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(_option ads (_switch ON))
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(_option selected_syn_tool_opt (_integer 2))
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(_db_output
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(_file "synthesize/Top_syn.adf"
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(_format adif)
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(_timespec "2023-12-31T15:14:07")
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)
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)
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(_output
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(_file "synthesize/Top_syn.vm"
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(_format structural_verilog)
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(_timespec "2023-12-31T15:14:07")
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)
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(_file "synthesize/Top.snr"
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(_format text)
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(_timespec "2023-12-31T15:14:07")
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)
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(_file "synthesize/snr.db"
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(_format text)
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(_timespec "2023-12-31T15:14:07")
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)
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)
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)
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(_widget wgt_tech_view
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(_attribute _click_to_run (_switch ON))
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)
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(_widget wgt_map_constraint
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)
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(_widget wgt_my_fic_src
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)
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(_widget wgt_inserter_gui_view
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(_attribute _click_to_run (_switch ON))
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)
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)
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(_task tsk_devmap
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(_command cmd_devmap
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(_gci_state (_integer 2))
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(_db_output
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(_file "device_map/Top_map.adf"
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(_format adif)
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(_timespec "2023-12-31T15:14:09")
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)
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)
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(_output
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(_file "device_map/Top_dmr.prt"
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(_format text)
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(_timespec "2023-12-31T15:14:09")
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)
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(_file "device_map/Top.dmr"
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(_format text)
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(_timespec "2023-12-31T15:14:09")
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)
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(_file "device_map/dmr.db"
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(_format text)
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(_timespec "2023-12-31T15:14:09")
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)
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)
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)
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(_widget wgt_edit_placement_cons
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(_attribute _click_to_run (_switch ON))
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(_input
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(_file "device_map/led_test.pcf"
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(_format pcf)
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(_timespec "2023-12-31T15:14:09")
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)
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)
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)
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(_widget wgt_edit_route_cons
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(_attribute _click_to_run (_switch ON))
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)
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)
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(_task tsk_pnr
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(_command cmd_pnr
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(_gci_state (_integer 2))
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(_db_output
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(_file "place_route/Top_pnr.adf"
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(_format adif)
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(_timespec "2023-12-31T15:14:13")
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)
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)
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(_output
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(_file "place_route/Top.prr"
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(_format text)
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(_timespec "2023-12-31T15:14:13")
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)
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(_file "place_route/Top_prr.prt"
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(_format text)
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(_timespec "2023-12-31T15:14:13")
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)
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(_file "place_route/clock_utilization.txt"
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(_format text)
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(_timespec "2023-12-31T15:14:12")
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)
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(_file "place_route/Top_plc.adf"
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(_format adif)
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(_timespec "2023-12-31T15:14:12")
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)
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(_file "place_route/Top_pnr.netlist"
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(_format text)
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(_timespec "2023-12-31T15:14:13")
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)
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(_file "place_route/prr.db"
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(_format text)
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(_timespec "2023-12-31T15:14:14")
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)
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)
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)
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(_widget wgt_power_calculator
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(_attribute _click_to_run (_switch ON))
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)
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(_widget wgt_timing_analysis
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(_attribute _click_to_run (_switch ON))
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)
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(_command cmd_report_post_pnr_timing
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(_gci_state (_integer 0))
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(_attribute _auto_exe_lock (_switch OFF))
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)
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(_widget wgt_arch_browser
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(_attribute _click_to_run (_switch ON))
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)
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(_command cmd_report_power
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(_gci_state (_integer 0))
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(_attribute _auto_exe_lock (_switch OFF))
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(_attribute _auto_exe (_switch OFF))
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)
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(_command cmd_gen_netlist
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(_gci_state (_integer 0))
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(_attribute _auto_exe_lock (_switch OFF))
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(_attribute _auto_exe (_switch OFF))
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)
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)
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(_task tsk_gen_bitstream
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(_command cmd_gen_bitstream
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(_gci_state (_integer 0))
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)
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)
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)
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