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208 lines
6.9 KiB
208 lines
6.9 KiB
module src_timecode_parser #(
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parameter REG_START_ADD = 0
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) (
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input clk, //clock input
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input rst_n, //asynchronous reset input, low active
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//regbus interface
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output reg [31:0] addr,
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input [31:0] wr_data,
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input wr_en,
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inout wire [31:0] rd_data, //received serial data
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// 输入
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input timecode_signal_in,
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//输出
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output wire timecode_signal_orgin_output, //ttl原始数据
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output wire timecode_freq_trigger_signal
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);
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/*******************************************************************************
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* 寄存器读写 *
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*******************************************************************************/
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//
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// @功能:
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// 1. 采样TIMECODE信号
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// 2. 转发TIMECODE信号
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// 3. TIMECODE信号成功解析
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// 4. TIMECODE采样计数
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//
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// @寄存器列表:
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// 地址 读写 默认 描述
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// 0x00 wr 0x0 timecode bit周期
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// 0x01 r 0x0 flag bit[0]:timecode_ready_flag
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// 0x02 r 0x0 timecode [31:0]
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// 0x03 r 0x0 timecode [63:32]
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// 0x04 r 0x0 timecode_ready_signal_pluse_width //识别到一帧timecode信号后，输出一个脉冲信号，用于同步其他模块
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parameter REG_TIMECODE_BIT_PERIOD_ADD = REG_START_ADD + 0; //timecode bit周期寄存器地址
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parameter ADD_NUM = 5; //寄存器数量
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parameter REG_END_ADD = REG_START_ADD + ADD_NUM - 1; //寄存器结束地址
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reg [31:0] register[REG_START_ADD:REG_END_ADD];
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integer i;
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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for (i = 0; i < ADD_NUM; i = i + 1) begin
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register[i] <= 0;
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end
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end else begin
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if (wr_en && addr >= REG_START_ADD && addr <= REG_END_ADD) register[addr] <= wr_data;
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end
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end
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assign rd_data = (addr >= REG_START_ADD && addr <= REG_END_ADD) ? register[addr] : 31'bz;
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// 416us 500us 520us
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// 边沿触发--> 采样偏移同步
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//
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// 416us采用 160byte 采样到同步
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// 电平变化修正采样计数
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//
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// 配置:
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// 1. 制式
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// 2.
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// 边沿信号捕获
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reg [160-1:0] tc_bit_2x; //timecode 每1/2bit
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reg [79:0] tc_bit; //timecode 每1bit
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reg sample_signal; //采样信号
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reg [31:0] sample_time_cnt; //采样计数
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wire sample_time_calibrate_signal; //采样信号修正器
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reg time_code_signal_edge; //timecode原始信号的边沿信号，即timecode上升沿或者下降沿时，置1
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assign timecode_signal_in_a = timecode_signal_in; //
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reg timecode_signal_in_b; //
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reg tc_sync_signal_edge; // timecode捕获到同步信号时，置1，此时可以解析timecode信号，并将其存放到寄存中
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/*******************************************************************************
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* timecode边沿信号捕获 *
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*******************************************************************************/
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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timecode_signal_in_b <= 0;
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end else begin
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timecode_signal_in_b <= timecode_signal_in_a;
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end
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end
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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time_code_signal_edge <= 0;
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end else begin
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if (timecode_signal_in_a != timecode_signal_in_b) begin
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time_code_signal_edge <= 1;
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end else begin
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time_code_signal_edge <= 0;
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end
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end
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end
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assign sample_time_calibrate_signal = time_code_signal_edge;
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/*******************************************************************************
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* BIT信号映射 *
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*******************************************************************************/
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//
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// 采样点 采样点 采样点 采样点
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// + + + +
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// ___------------_______--------
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// 0 1
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// timecode的每个bit要通过两个点进行判断，所以需要2x的采样率
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//
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always @(*) begin
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for (i = 0; i < 79; i = i + 1) begin
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tc_bit[i] = !tc_bit_2x[i*2] & tc_bit_2x[i*2+1];
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end
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end
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/*******************************************************************************
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* 采样信号生成器 *
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*******************************************************************************/
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//
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// 1. 当捕获到timecode原始信号的边沿时，校准采样信号计数器
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// 2. 当采样信号计数器到达采样点时，输出采样信号
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// 3. 当采样信号计数器到达2倍采样点时，重置采样信号计数器
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//
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assign timecode_sample_cnt_reset_signal = (
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sample_time_calibrate_signal||
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sample_time_cnt >= (register[REG_TIMECODE_BIT_PERIOD_ADD] << 1)
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);
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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sample_time_cnt <= 0;
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sample_signal <= 0;
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end else begin
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if (timecode_sample_cnt_reset_signal) begin
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sample_time_cnt <= 0;
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sample_signal <= 0;
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end else if (sample_time_cnt == register[REG_TIMECODE_BIT_PERIOD_ADD]) begin
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sample_time_cnt <= sample_time_cnt + 1;
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sample_signal <= 1;
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end else begin
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sample_time_cnt <= sample_time_cnt + 1;
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sample_signal <= 0;
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end
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end
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end
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//
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// 根据sample_signal捕获timecode信号
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//
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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tc_bit_2x <= 0;
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end else begin
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if (sample_signal) begin
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tc_bit_2x <= {tc_bit_2x[158:0], timecode_signal_in};
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end else begin
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tc_bit_2x <= tc_bit_2x;
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end
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end
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end
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/*******************************************************************************
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* tc_sync_signal_edge *
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*******************************************************************************/
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// ___------------_______--------
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// 0 1
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//
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// 捕获timecode同步信号
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//
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// 同步信号
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// 0011_1111_11111_1101
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// 1111_0101__0101_0101__0101_0101__0101_1101
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//
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reg [31:0] sync_code_pattern = 32'b1111_0101__0101_0101__0101_0101__0101_1101;
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assign tc_sync_signal = (tc_bit == sync_code_pattern);
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reg tc_sync_signal_b;
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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tc_sync_signal_b <= 0;
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end else begin
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tc_sync_signal_b <= tc_sync_signal;
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if (tc_sync_signal & !tc_sync_signal_b) begin
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tc_sync_signal_edge <= 1;
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end else begin
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tc_sync_signal_edge <= 0;
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end
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end
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end
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assign timecode_freq_trigger_signal = tc_sync_signal_edge;
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endmodule
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