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299 lines
10 KiB
299 lines
10 KiB
// Created by IP Generator (Version 2021.1-SP7 build 86875)
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//////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (c) 2019 PANGO MICROSYSTEMS, INC
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// ALL RIGHTS REVERVED.
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//
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// THE SOURCE CODE CONTAINED HEREIN IS PROPRIETARY TO PANGO MICROSYSTEMS, INC.
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// IT SHALL NOT BE REPRODUCED OR DISCLOSED IN WHOLE OR IN PART OR USED BY
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// PARTIES WITHOUT WRITTEN AUTHORIZATION FROM THE OWNER.
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//
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//////////////////////////////////////////////////////////////////////////////
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//
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// Library:
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// Filename:SPLL.v
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//////////////////////////////////////////////////////////////////////////////
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module SPLL (
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clkin1,
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clkout0,
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clkout1,
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clkout2,
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pll_lock
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);
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localparam real CLKIN_FREQ = 50.0;
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localparam integer STATIC_RATIOI = 2;
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localparam integer STATIC_RATIO0 = 24;
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localparam integer STATIC_RATIO1 = 60;
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localparam integer STATIC_RATIO2 = 120;
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localparam integer STATIC_RATIO3 = 16;
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localparam integer STATIC_RATIO4 = 16;
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localparam integer STATIC_RATIOF = 24;
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localparam integer STATIC_DUTY0 = 24;
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localparam integer STATIC_DUTY1 = 60;
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localparam integer STATIC_DUTY2 = 120;
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localparam integer STATIC_DUTY3 = 16;
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localparam integer STATIC_DUTY4 = 16;
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localparam integer STATIC_DUTYF = 24;
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localparam integer STATIC_PHASE0 = 16;
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localparam integer STATIC_PHASE1 = 16;
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localparam integer STATIC_PHASE2 = 16;
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localparam integer STATIC_PHASE3 = 16;
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localparam integer STATIC_PHASE4 = 16;
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localparam CLK_CAS1_EN = "FALSE";
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localparam CLK_CAS2_EN = "FALSE";
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localparam CLK_CAS3_EN = "FALSE";
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localparam CLK_CAS4_EN = "FALSE";
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localparam CLKIN_BYPASS_EN = "FALSE";
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localparam CLKOUT0_GATE_EN = "FALSE";
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localparam CLKOUT0_EXT_GATE_EN = "FALSE";
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localparam CLKOUT1_GATE_EN = "FALSE";
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localparam CLKOUT2_GATE_EN = "FALSE";
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localparam CLKOUT3_GATE_EN = "FALSE";
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localparam CLKOUT4_GATE_EN = "FALSE";
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localparam FBMODE = "FALSE";
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localparam integer FBDIV_SEL = 0;
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localparam BANDWIDTH = "OPTIMIZED";
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localparam PFDEN_EN = "FALSE";
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localparam VCOCLK_DIV2 = 1'b0;
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localparam DYNAMIC_RATIOI_EN = "FALSE";
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localparam DYNAMIC_RATIO0_EN = "FALSE";
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localparam DYNAMIC_RATIO1_EN = "FALSE";
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localparam DYNAMIC_RATIO2_EN = "FALSE";
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localparam DYNAMIC_RATIO3_EN = "FALSE";
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localparam DYNAMIC_RATIO4_EN = "FALSE";
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localparam DYNAMIC_RATIOF_EN = "FALSE";
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localparam DYNAMIC_DUTY0_EN = "FALSE";
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localparam DYNAMIC_DUTY1_EN = "FALSE";
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localparam DYNAMIC_DUTY2_EN = "FALSE";
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localparam DYNAMIC_DUTY3_EN = "FALSE";
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localparam DYNAMIC_DUTY4_EN = "FALSE";
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localparam DYNAMIC_DUTYF_EN = "FALSE";
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localparam PHASE_ADJUST0_EN = "TRUE";
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localparam PHASE_ADJUST1_EN = (CLK_CAS1_EN == "TRUE") ? "FALSE" : "TRUE";
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localparam PHASE_ADJUST2_EN = (CLK_CAS2_EN == "TRUE") ? "FALSE" : "TRUE";
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localparam PHASE_ADJUST3_EN = (CLK_CAS3_EN == "TRUE") ? "FALSE" : "TRUE";
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localparam PHASE_ADJUST4_EN = (CLK_CAS4_EN == "TRUE") ? "FALSE" : "TRUE";
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localparam DYNAMIC_PHASE0_EN = "FALSE";
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localparam DYNAMIC_PHASE1_EN = "FALSE";
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localparam DYNAMIC_PHASE2_EN = "FALSE";
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localparam DYNAMIC_PHASE3_EN = "FALSE";
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localparam DYNAMIC_PHASE4_EN = "FALSE";
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localparam DYNAMIC_PHASEF_EN = "FALSE";
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localparam integer STATIC_PHASEF = 16;
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localparam CLK_CAS0_EN = "FALSE";
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localparam integer CLKOUT5_SEL = 0;
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localparam CLKOUT5_GATE_EN = "FALSE";
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localparam INTERNAL_FB = (FBMODE == "FALSE") ? "ENABLE":"DISABLE";
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localparam EXTERNAL_FB = (FBMODE == "FALSE") ? "DISABLE":
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(FBDIV_SEL == 0) ? "CLKOUT0":
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(FBDIV_SEL == 1) ? "CLKOUT1":
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(FBDIV_SEL == 2) ? "CLKOUT2":
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(FBDIV_SEL == 3) ? "CLKOUT3":
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(FBDIV_SEL == 4) ? "CLKOUT4":"DISABLE";
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localparam RSTODIV_ENABLE = "FALSE";
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localparam SIM_DEVICE = "PGL22G";
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input clkin1;
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output clkout0;
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output clkout1;
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output clkout2;
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output pll_lock;
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wire clkout0;
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wire clkout0_2pad;
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wire clkout1;
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wire clkout2;
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wire clkout3;
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wire clkout4;
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wire clkout5;
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wire clkswitch_flag;
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wire pll_lock;
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wire clkin1;
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wire clkin2;
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wire clkfb;
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wire clkin_sel;
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wire clkin_sel_en;
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wire pfden;
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wire clkout0_gate;
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wire clkout0_2pad_gate;
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wire clkout1_gate;
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wire clkout2_gate;
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wire clkout3_gate;
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wire clkout4_gate;
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wire clkout5_gate;
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wire [9:0] dyn_idiv;
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wire [9:0] dyn_odiv0;
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wire [9:0] dyn_odiv1;
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wire [9:0] dyn_odiv2;
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wire [9:0] dyn_odiv3;
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wire [9:0] dyn_odiv4;
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wire [9:0] dyn_fdiv;
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wire [9:0] dyn_duty0;
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wire [9:0] dyn_duty1;
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wire [9:0] dyn_duty2;
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wire [9:0] dyn_duty3;
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wire [9:0] dyn_duty4;
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wire [12:0] dyn_phase0;
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wire [12:0] dyn_phase1;
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wire [12:0] dyn_phase2;
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wire [12:0] dyn_phase3;
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wire [12:0] dyn_phase4;
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wire pll_pwd;
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wire pll_rst;
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wire rstodiv;
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wire icp_base;
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wire [3:0] icp_sel;
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wire [2:0] lpfres_sel;
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wire cripple_sel;
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wire [2:0] phase_sel;
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wire phase_dir;
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wire phase_step_n;
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wire load_phase;
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wire [6:0] dyn_mdiv;
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assign clkin2 = 1'b0;
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assign clkin_sel = 1'b0;
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assign clkin_sel_en = 1'b0;
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assign pll_pwd = 1'b0;
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assign pll_rst = 1'b0;
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assign rstodiv = 1'b0;
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GTP_PLL_E1 #(
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.CLKIN_FREQ(CLKIN_FREQ),
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.PFDEN_EN(PFDEN_EN),
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.VCOCLK_DIV2(VCOCLK_DIV2),
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.DYNAMIC_RATIOI_EN(DYNAMIC_RATIOI_EN),
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.DYNAMIC_RATIO0_EN(DYNAMIC_RATIO0_EN),
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.DYNAMIC_RATIO1_EN(DYNAMIC_RATIO1_EN),
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.DYNAMIC_RATIO2_EN(DYNAMIC_RATIO2_EN),
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.DYNAMIC_RATIO3_EN(DYNAMIC_RATIO3_EN),
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.DYNAMIC_RATIO4_EN(DYNAMIC_RATIO4_EN),
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.DYNAMIC_RATIOF_EN(DYNAMIC_RATIOF_EN),
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.STATIC_RATIOI(STATIC_RATIOI),
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.STATIC_RATIO0(STATIC_RATIO0),
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.STATIC_RATIO1(STATIC_RATIO1),
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.STATIC_RATIO2(STATIC_RATIO2),
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.STATIC_RATIO3(STATIC_RATIO3),
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.STATIC_RATIO4(STATIC_RATIO4),
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.STATIC_RATIOF(STATIC_RATIOF),
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.DYNAMIC_DUTY0_EN(DYNAMIC_DUTY0_EN),
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.DYNAMIC_DUTY1_EN(DYNAMIC_DUTY1_EN),
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.DYNAMIC_DUTY2_EN(DYNAMIC_DUTY2_EN),
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.DYNAMIC_DUTY3_EN(DYNAMIC_DUTY3_EN),
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.DYNAMIC_DUTY4_EN(DYNAMIC_DUTY4_EN),
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.DYNAMIC_DUTYF_EN(DYNAMIC_DUTYF_EN),
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.STATIC_DUTY0(STATIC_DUTY0),
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.STATIC_DUTY1(STATIC_DUTY1),
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.STATIC_DUTY2(STATIC_DUTY2),
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.STATIC_DUTY3(STATIC_DUTY3),
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.STATIC_DUTY4(STATIC_DUTY4),
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.STATIC_DUTYF(STATIC_DUTYF),
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.PHASE_ADJUST0_EN(PHASE_ADJUST0_EN),
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.PHASE_ADJUST1_EN(PHASE_ADJUST1_EN),
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.PHASE_ADJUST2_EN(PHASE_ADJUST2_EN),
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.PHASE_ADJUST3_EN(PHASE_ADJUST3_EN),
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.PHASE_ADJUST4_EN(PHASE_ADJUST4_EN),
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.DYNAMIC_PHASE0_EN(DYNAMIC_PHASE0_EN),
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.DYNAMIC_PHASE1_EN(DYNAMIC_PHASE1_EN),
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.DYNAMIC_PHASE2_EN(DYNAMIC_PHASE2_EN),
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.DYNAMIC_PHASE3_EN(DYNAMIC_PHASE3_EN),
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.DYNAMIC_PHASE4_EN(DYNAMIC_PHASE4_EN),
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.DYNAMIC_PHASEF_EN(DYNAMIC_PHASEF_EN),
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.STATIC_PHASE0(STATIC_PHASE0[2:0]),
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.STATIC_PHASE1(STATIC_PHASE1[2:0]),
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.STATIC_PHASE2(STATIC_PHASE2[2:0]),
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.STATIC_PHASE3(STATIC_PHASE3[2:0]),
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.STATIC_PHASE4(STATIC_PHASE4[2:0]),
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.STATIC_PHASEF(STATIC_PHASEF[2:0]),
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.STATIC_CPHASE0(STATIC_PHASE0[12:3]),
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.STATIC_CPHASE1(STATIC_PHASE1[12:3]),
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.STATIC_CPHASE2(STATIC_PHASE2[12:3]),
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.STATIC_CPHASE3(STATIC_PHASE3[12:3]),
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.STATIC_CPHASE4(STATIC_PHASE4[12:3]),
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.STATIC_CPHASEF(STATIC_PHASEF[12:3]),
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.CLK_CAS0_EN(CLK_CAS0_EN),
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.CLK_CAS1_EN(CLK_CAS1_EN),
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.CLK_CAS2_EN(CLK_CAS2_EN),
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.CLK_CAS3_EN(CLK_CAS3_EN),
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.CLK_CAS4_EN(CLK_CAS4_EN),
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.CLKOUT5_SEL(CLKOUT5_SEL),
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.CLKIN_BYPASS_EN(CLKIN_BYPASS_EN),
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.CLKOUT0_SYN_EN(CLKOUT0_GATE_EN),
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.CLKOUT0_EXT_SYN_EN(CLKOUT0_EXT_GATE_EN),
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.CLKOUT1_SYN_EN(CLKOUT1_GATE_EN),
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.CLKOUT2_SYN_EN(CLKOUT2_GATE_EN),
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.CLKOUT3_SYN_EN(CLKOUT3_GATE_EN),
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.CLKOUT4_SYN_EN(CLKOUT4_GATE_EN),
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.CLKOUT5_SYN_EN(CLKOUT5_GATE_EN),
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.INTERNAL_FB(INTERNAL_FB),
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.EXTERNAL_FB(EXTERNAL_FB),
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.RSTODIV_PHASE_EN(RSTODIV_ENABLE),
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.SIM_DEVICE(SIM_DEVICE),
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.BANDWIDTH(BANDWIDTH)
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) u_pll_e1 (
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.CLKOUT0(clkout0),
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.CLKOUT0_EXT(clkout0_2pad),
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.CLKOUT1(clkout1),
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.CLKOUT2(clkout2),
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.CLKOUT3(clkout3),
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.CLKOUT4(clkout4),
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.CLKOUT5(clkout5),
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.CLKSWITCH_FLAG(clkswitch_flag),
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.LOCK(pll_lock),
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.CLKIN1(clkin1),
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.CLKIN2(clkin2),
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.CLKFB(clkfb),
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.CLKIN_SEL(clkin_sel),
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.CLKIN_SEL_EN(clkin_sel_en),
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.PFDEN(pfden),
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.RATIOI(dyn_idiv),
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.RATIO0(dyn_odiv0),
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.RATIO1(dyn_odiv1),
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.RATIO2(dyn_odiv2),
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.RATIO3(dyn_odiv3),
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.RATIO4(dyn_odiv4),
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.RATIOF(dyn_fdiv),
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.DUTY0(dyn_duty0),
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.DUTY1(dyn_duty1),
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.DUTY2(dyn_duty2),
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.DUTY3(dyn_duty3),
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.DUTY4(dyn_duty4),
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.DUTYF(),
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.PHASE0(dyn_phase0[2:0]),
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.PHASE1(dyn_phase1[2:0]),
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.PHASE2(dyn_phase2[2:0]),
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.PHASE3(dyn_phase3[2:0]),
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.PHASE4(dyn_phase4[2:0]),
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.PHASEF(),
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.CPHASE0(dyn_phase0[12:3]),
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.CPHASE1(dyn_phase1[12:3]),
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.CPHASE2(dyn_phase2[12:3]),
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.CPHASE3(dyn_phase3[12:3]),
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.CPHASE4(dyn_phase4[12:3]),
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.CPHASEF(),
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.CLKOUT0_SYN(clkout0_gate),
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.CLKOUT0_EXT_SYN(clkout0_2pad_gate),
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.CLKOUT1_SYN(clkout1_gate),
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.CLKOUT2_SYN(clkout2_gate),
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.CLKOUT3_SYN(clkout3_gate),
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.CLKOUT4_SYN(clkout4_gate),
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.CLKOUT5_SYN(clkout5_gate),
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.PLL_PWD(pll_pwd),
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.RST(pll_rst),
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.RSTODIV_PHASE(rstodiv)
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);
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endmodule
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