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17 lines
665 B
17 lines
665 B
IP Generator (Version 2021.1-SP7 build 86875)
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Check out license ...
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Start generating at 2024-01-11 09:39
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Instance: SPLL (D:\workspace\fpga_demo\led_test\ipcore\SPLL\SPLL.idf)
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IP: PLL (1.5)
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Part: Logos-PGL22G-MBG324--6
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Create directory 'rtl' ...
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Copy 'ipml_pll_wrapper_v1_4.v.xml' ...
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Compile file 'ipml_pll_wrapper_v1_4.v.xml' to 'SPLL.v' ...
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Found top module 'SPLL' in file 'SPLL.v'.
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Copy 'ipml_pll_wrapper_v1_4_tb.v.xml' ...
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Compile file 'ipml_pll_wrapper_v1_4_tb.v.xml' to 'SPLL_tb.v' ...
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Create template file 'SPLL_tmpl.v' ...
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Create template file 'SPLL_tmpl.vhdl' ...
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There is 1 source file to synthesize.
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Synthesis is disabled.
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Done: 0 error(s), 0 warning(s)
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