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50 lines
819 B
50 lines
819 B
`timescale 1ns / 1ns
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module test_top;
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// Inputs
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reg clk_50m;
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reg rst_n;
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wire rxclk_en;
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wire txclk_en;
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wire [3:0] led;
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wire test_io3;
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wire test_io4;
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wire test_io5;
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wire test_io6;
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wire test_io7;
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wire test_io8;
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wire test_io9;
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wire test_io10;
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wire test_io11;
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Top top_impl (
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.sys_clk(clk_50m),
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.rst_n(rst_n),
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.led(led),
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.test_io3(test_io3),
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.test_io4(test_io4),
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.test_io5(test_io5),
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.test_io6(test_io6),
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.test_io7(test_io7),
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.test_io8(test_io8),
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.test_io9(test_io9),
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.test_io10(test_io10),
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.test_io11(test_io11)
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);
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initial begin
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// Initialize Inputs
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clk_50m = 0;
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rst_n = 0;
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#100;
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rst_n = 1;
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#15;
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#300000;
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$stop;
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end
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always #10 clk_50m = ~clk_50m; //20ns 50MHZ
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endmodule
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