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66 lines
1.2 KiB
66 lines
1.2 KiB
`timescale 1ns / 1ns
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module test_uart_reg_reader;
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// Inputs
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reg clk_50m;
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reg rst_n;
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reg [31:0] reg_data;
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wire [31:0] reg_add;
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wire reg_add_valid;
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reg uart_rx_pin;
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wire uart_tx_pin;
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uart_reg_reader uart_reg_reader_impl (
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.clk(clk_50m),
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.rst_n(rst_n),
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.reg_data(reg_data),
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.reg_add(reg_add),
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.reg_add_valid(reg_add_valid),
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.uart_rx_pin(uart_rx_pin),
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.uart_tx_pin(uart_tx_pin)
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);
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initial begin
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// Initialize Inputs
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clk_50m = 0;
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rst_n = 0;
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reg_data = 31'h11223344;
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uart_rx_pin = 1;
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#10;
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rst_n = 1;
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#1000;
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uart_rx_pin = 1;
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#(8.680 * 1000);
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uart_rx_pin = 0;
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#(8.680 * 1000);
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uart_rx_pin = 1;
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#(8.680 * 1000);
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uart_rx_pin = 0;
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#(8.680 * 1000);
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uart_rx_pin = 1;
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#(8.680 * 1000);
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uart_rx_pin = 0;
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#(8.680 * 1000);
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uart_rx_pin = 1;
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#(8.680 * 1000);
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uart_rx_pin = 0;
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#(8.680 * 1000);
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uart_rx_pin = 1;
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#(8.680 * 1000);
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uart_rx_pin = 0;
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#(8.680 * 1000);
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uart_rx_pin = 1;
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#(8.680 * 1000);
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uart_rx_pin = 0;
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#(8.680 * 1000);
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uart_rx_pin = 1;
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#(100 * 8.680 * 1000);
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$stop;
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end
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always #10 clk_50m = ~clk_50m; //20ns 50MHZ
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endmodule
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