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@ -1436,9 +1436,14 @@ sub decode_ddr3_sdram($) |
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# more timing information |
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# more timing information |
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prints("Timing Parameters"); |
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prints("Timing Parameters"); |
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printl("Minimum Cycle Time (tCK)", tns3($ctime)); |
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printl("Minimum CAS Latency Time (tAA)", tns3($taa)); |
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printl("Minimum Write Recovery time (tWR)", tns3($bytes->[17] * $mtb)); |
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printl("Minimum Write Recovery time (tWR)", tns3($bytes->[17] * $mtb)); |
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printl("Minimum RAS# to CAS# Delay (tRCD)", tns3($trcd)); |
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printl("Minimum Row Active to Row Active Delay (tRRD)", |
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printl("Minimum Row Active to Row Active Delay (tRRD)", |
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tns3($bytes->[19] * $mtb)); |
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tns3($bytes->[19] * $mtb)); |
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printl("Minimum Row Precharge Delay (tRP)", tns3($trp)); |
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printl("Minimum Active to Precharge Delay (tRAS)", tns3($tras)); |
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printl("Minimum Active to Auto-Refresh Delay (tRC)", |
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printl("Minimum Active to Auto-Refresh Delay (tRC)", |
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tns3(ddr3_mtb_ftb((($bytes->[21] & 0xf0) << 4) + $bytes->[23], $bytes->[38], $mtb, $ftb))); |
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tns3(ddr3_mtb_ftb((($bytes->[21] & 0xf0) << 4) + $bytes->[23], $bytes->[38], $mtb, $ftb))); |
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printl("Minimum Recovery Delay (tRFC)", |
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printl("Minimum Recovery Delay (tRFC)", |
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