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@ -510,6 +510,21 @@ sub value_or_undefined |
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return $value; |
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} |
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# Common to SDR, DDR and DDR2 SDRAM |
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sub sdram_voltage_interface_level($) |
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{ |
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my @levels = ( |
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"TTL (5V tolerant)", # 0 |
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"LVTTL (not 5V tolerant)", # 1 |
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"HSTL 1.5V", # 2 |
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"SSTL 3.3V", # 3 |
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"SSTL 2.5V", # 4 |
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"SSTL 1.8V", # 5 |
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); |
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return ($_[0] < @levels) ? $levels[$_[0]] : "Undefined!"; |
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} |
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# Parameter: EEPROM bytes 0-127 (using 3-62) |
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sub decode_sdr_sdram($) |
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{ |
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@ -578,14 +593,8 @@ sub decode_sdr_sdram($) |
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else { $temp = ($bytes->[7] * 256) + $bytes->[6]; } |
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printl("Data Width", $temp); |
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if ($bytes->[8] == 0) { $temp = "5.0 Volt/TTL"; } |
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elsif ($bytes->[8] == 1) { $temp = "LVTTL"; } |
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elsif ($bytes->[8] == 2) { $temp = "HSTL 1.5"; } |
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elsif ($bytes->[8] == 3) { $temp = "SSTL 3.3"; } |
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elsif ($bytes->[8] == 4) { $temp = "SSTL 2.5"; } |
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elsif ($bytes->[8] == 255) { $temp = "New Table"; } |
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else { $temp = "Undefined!"; } |
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printl("Module Interface Signal Levels", $temp); |
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printl("Voltage Interface Level", |
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sdram_voltage_interface_level($bytes->[8])); |
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if ($bytes->[11] == 0) { $temp = "No Parity"; } |
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elsif ($bytes->[11] == 1) { $temp = "Parity"; } |
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@ -809,6 +818,9 @@ sub decode_ddr_sdram($) |
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$bytes->[5] . ", " . $bytes->[17]); |
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} |
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printl("Voltage Interface Level", |
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sdram_voltage_interface_level($bytes->[8])); |
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my $highestCAS = 0; |
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my %cas; |
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for ($ii = 0; $ii < 7; $ii++) { |
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@ -1001,9 +1013,8 @@ sub decode_ddr2_sdram($) |
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printl("DRAM Package", $bytes->[5] & 0x10 ? "Stack" : "Planar"); |
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my @volts = ("TTL (5V Tolerant)", "LVTTL", "HSTL 1.5V", |
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"SSTL 3.3V", "SSTL 2.5V", "SSTL 1.8V", "TBD"); |
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printl("Voltage Interface Level", $volts[$bytes->[8]]); |
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printl("Voltage Interface Level", |
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sdram_voltage_interface_level($bytes->[8])); |
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printl("Refresh Rate", ddr2_refresh_rate($bytes->[12])); |
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