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@ -766,6 +766,7 @@ sub decode_sdr_sdram($) |
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printl_cond(defined $cycle_time, "Cycle Time", $cycle_time); |
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printl_cond(defined $access_time, "Access Time", $access_time); |
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prints("Attributes"); |
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$temp = ""; |
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if ($bytes->[21] & 1) { $temp .= "Buffered Address/Control Inputs\n"; } |
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if ($bytes->[21] & 2) { $temp .= "Registered Address/Control Inputs\n"; } |
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@ -775,8 +776,7 @@ sub decode_sdr_sdram($) |
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if ($bytes->[21] & 32) { $temp .= "Differential Clock Input\n"; } |
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if ($bytes->[21] & 64) { $temp .= "Redundant Row Address\n"; } |
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if ($bytes->[21] & 128) { $temp .= "Undefined (bit 7)\n"; } |
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if ($bytes->[21] == 0) { $temp .= "(None Reported)\n"; } |
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printl("SDRAM Module Attributes", $temp); |
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printl_cond($bytes->[21], "SDRAM Module Attributes", $temp); |
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$temp = ""; |
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if ($bytes->[22] & 1) { $temp .= "Supports Early RAS# Recharge\n"; } |
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@ -791,6 +791,7 @@ sub decode_sdr_sdram($) |
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if ($bytes->[22] & 128) { $temp .= "Undefined (bit 7)\n"; } |
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printl("SDRAM Device Attributes (General)", $temp); |
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prints("Timing Parameters"); |
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printl("Minimum Row Precharge Time", |
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value_or_undefined($bytes->[27], "ns")); |
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