diff --git a/CHANGES b/CHANGES index 8f4d015..bdaa767 100644 --- a/CHANGES +++ b/CHANGES @@ -13,6 +13,7 @@ SVN HEAD Print extra timing values of DDR SDRAM Print DDR core timings for all supported CAS values Print DDR2 equivalent speed of tCK max + Don't print undefined DDR2 SDRAM timings i2cdetect: Do a best effort detection if functionality is missing i2c-dev.h: Minimize differences with kernel flavor Move SMBus helper functions to include/i2c/smbus.h diff --git a/eeprom/decode-dimms b/eeprom/decode-dimms index 9115ded..9d1ed3e 100755 --- a/eeprom/decode-dimms +++ b/eeprom/decode-dimms @@ -5,7 +5,7 @@ # Copyright 1998, 1999 Philip Edelbrock # modified by Christian Zuckschwerdt # modified by Burkart Lingner -# Copyright (C) 2005-2011 Jean Delvare +# Copyright (C) 2005-2012 Jean Delvare # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -1194,29 +1194,51 @@ sub decode_ddr2_sdram($) # more timing information prints("Timing Parameters"); - printl("Address/Command Setup Time Before Clock (tIS)", - tns(ddr2_sdram_atime($bytes->[32]))); - printl("Address/Command Hold Time After Clock (tIH)", - tns(ddr2_sdram_atime($bytes->[33]))); - printl("Data Input Setup Time Before Strobe (tDS)", - tns(ddr2_sdram_atime($bytes->[34]))); - printl("Data Input Hold Time After Strobe (tDH)", - tns(ddr2_sdram_atime($bytes->[35]))); + # According to the JEDEC standard, the four timings below can't be less + # than 0.1 ns, however we've seen memory modules code such values so + # handle them properly. + printl_cond($bytes->[32] && $bytes->[32] != 0xff, + "Address/Command Setup Time Before Clock (tIS)", + tns(ddr2_sdram_atime($bytes->[32]))); + printl_cond($bytes->[33] && $bytes->[33] != 0xff, + "Address/Command Hold Time After Clock (tIH)", + tns(ddr2_sdram_atime($bytes->[33]))); + printl_cond($bytes->[34] && $bytes->[34] != 0xff, + "Data Input Setup Time Before Strobe (tDS)", + tns(ddr2_sdram_atime($bytes->[34]))); + printl_cond($bytes->[35] && $bytes->[35] != 0xff, + "Data Input Hold Time After Strobe (tDH)", + tns(ddr2_sdram_atime($bytes->[35]))); + printl("Minimum Row Precharge Delay (tRP)", tns($trp)); - printl("Minimum Row Active to Row Active Delay (tRRD)", - tns($bytes->[28]/4)); + printl_cond($bytes->[28] & 0xfc, + "Minimum Row Active to Row Active Delay (tRRD)", + tns($bytes->[28]/4)); printl("Minimum RAS# to CAS# Delay (tRCD)", tns($trcd)); printl("Minimum RAS# Pulse Width (tRAS)", tns($tras)); - printl("Write Recovery Time (tWR)", tns($bytes->[36]/4)); - printl("Minimum Write to Read CMD Delay (tWTR)", tns($bytes->[37]/4)); - printl("Minimum Read to Pre-charge CMD Delay (tRTP)", tns($bytes->[38]/4)); - printl("Minimum Active to Auto-refresh Delay (tRC)", - tns(ddr2_sdram_rtime($bytes->[41], 0, ($bytes->[40] >> 4) & 7))); - printl("Minimum Recovery Delay (tRFC)", - tns(ddr2_sdram_rtime($bytes->[42], $bytes->[40] & 1, - ($bytes->[40] >> 1) & 7))); - printl("Maximum DQS to DQ Skew (tDQSQ)", tns($bytes->[44]/100)); - printl("Maximum Read Data Hold Skew (tQHS)", tns($bytes->[45]/100)); + printl_cond($bytes->[36] & 0xfc, + "Write Recovery Time (tWR)", + tns($bytes->[36]/4)); + printl_cond($bytes->[37] & 0xfc, + "Minimum Write to Read CMD Delay (tWTR)", + tns($bytes->[37]/4)); + printl_cond($bytes->[38] & 0xfc, + "Minimum Read to Pre-charge CMD Delay (tRTP)", + tns($bytes->[38]/4)); + + printl_cond($bytes->[41] && $bytes->[41] != 0xff, + "Minimum Active to Auto-refresh Delay (tRC)", + tns(ddr2_sdram_rtime($bytes->[41], 0, + ($bytes->[40] >> 4) & 7))); + printl_cond($bytes->[42], + "Minimum Recovery Delay (tRFC)", + tns(ddr2_sdram_rtime($bytes->[42], $bytes->[40] & 1, + ($bytes->[40] >> 1) & 7))); + + printl_cond($bytes->[44], "Maximum DQS to DQ Skew (tDQSQ)", + tns($bytes->[44]/100)); + printl_cond($bytes->[45], "Maximum Read Data Hold Skew (tQHS)", + tns($bytes->[45]/100)); printl_cond($bytes->[46], "PLL Relock Time", $bytes->[46] . " us"); }