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@ -5,7 +5,7 @@ |
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# Copyright 1998, 1999 Philip Edelbrock <phil@netroedge.com> |
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# modified by Christian Zuckschwerdt <zany@triq.net> |
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# modified by Burkart Lingner <burkart@bollchen.de> |
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# Copyright (C) 2005-2011 Jean Delvare <khali@linux-fr.org> |
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# Copyright (C) 2005-2012 Jean Delvare <khali@linux-fr.org> |
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# |
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# This program is free software; you can redistribute it and/or modify |
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# it under the terms of the GNU General Public License as published by |
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@ -1194,29 +1194,51 @@ sub decode_ddr2_sdram($) |
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# more timing information |
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prints("Timing Parameters"); |
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printl("Address/Command Setup Time Before Clock (tIS)", |
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# According to the JEDEC standard, the four timings below can't be less |
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# than 0.1 ns, however we've seen memory modules code such values so |
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# handle them properly. |
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printl_cond($bytes->[32] && $bytes->[32] != 0xff, |
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"Address/Command Setup Time Before Clock (tIS)", |
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tns(ddr2_sdram_atime($bytes->[32]))); |
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printl("Address/Command Hold Time After Clock (tIH)", |
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printl_cond($bytes->[33] && $bytes->[33] != 0xff, |
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"Address/Command Hold Time After Clock (tIH)", |
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tns(ddr2_sdram_atime($bytes->[33]))); |
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printl("Data Input Setup Time Before Strobe (tDS)", |
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printl_cond($bytes->[34] && $bytes->[34] != 0xff, |
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"Data Input Setup Time Before Strobe (tDS)", |
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tns(ddr2_sdram_atime($bytes->[34]))); |
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printl("Data Input Hold Time After Strobe (tDH)", |
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printl_cond($bytes->[35] && $bytes->[35] != 0xff, |
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"Data Input Hold Time After Strobe (tDH)", |
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tns(ddr2_sdram_atime($bytes->[35]))); |
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printl("Minimum Row Precharge Delay (tRP)", tns($trp)); |
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printl("Minimum Row Active to Row Active Delay (tRRD)", |
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printl_cond($bytes->[28] & 0xfc, |
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"Minimum Row Active to Row Active Delay (tRRD)", |
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tns($bytes->[28]/4)); |
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printl("Minimum RAS# to CAS# Delay (tRCD)", tns($trcd)); |
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printl("Minimum RAS# Pulse Width (tRAS)", tns($tras)); |
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printl("Write Recovery Time (tWR)", tns($bytes->[36]/4)); |
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printl("Minimum Write to Read CMD Delay (tWTR)", tns($bytes->[37]/4)); |
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printl("Minimum Read to Pre-charge CMD Delay (tRTP)", tns($bytes->[38]/4)); |
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printl("Minimum Active to Auto-refresh Delay (tRC)", |
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tns(ddr2_sdram_rtime($bytes->[41], 0, ($bytes->[40] >> 4) & 7))); |
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printl("Minimum Recovery Delay (tRFC)", |
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printl_cond($bytes->[36] & 0xfc, |
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"Write Recovery Time (tWR)", |
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tns($bytes->[36]/4)); |
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printl_cond($bytes->[37] & 0xfc, |
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"Minimum Write to Read CMD Delay (tWTR)", |
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tns($bytes->[37]/4)); |
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printl_cond($bytes->[38] & 0xfc, |
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"Minimum Read to Pre-charge CMD Delay (tRTP)", |
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tns($bytes->[38]/4)); |
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printl_cond($bytes->[41] && $bytes->[41] != 0xff, |
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"Minimum Active to Auto-refresh Delay (tRC)", |
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tns(ddr2_sdram_rtime($bytes->[41], 0, |
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($bytes->[40] >> 4) & 7))); |
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printl_cond($bytes->[42], |
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"Minimum Recovery Delay (tRFC)", |
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tns(ddr2_sdram_rtime($bytes->[42], $bytes->[40] & 1, |
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($bytes->[40] >> 1) & 7))); |
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printl("Maximum DQS to DQ Skew (tDQSQ)", tns($bytes->[44]/100)); |
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printl("Maximum Read Data Hold Skew (tQHS)", tns($bytes->[45]/100)); |
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printl_cond($bytes->[44], "Maximum DQS to DQ Skew (tDQSQ)", |
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tns($bytes->[44]/100)); |
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printl_cond($bytes->[45], "Maximum Read Data Hold Skew (tQHS)", |
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tns($bytes->[45]/100)); |
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printl_cond($bytes->[46], "PLL Relock Time", $bytes->[46] . " us"); |
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} |
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