diff --git a/CHANGES b/CHANGES
index 4017d20..55f12fc 100644
--- a/CHANGES
+++ b/CHANGES
@@ -15,7 +15,7 @@ SVN HEAD
                 Print DDR and DDR2 core timings for all supported CAS values
                 Print DDR2 equivalent speed of tCK max
                 Don't print undefined DDR2 SDRAM timings
-		Print SDR, DDR and DDR2 core timings for all standard speeds
+		Print SDR, DDR, DDR2, DDR3 core timings for all standard speeds
                 Update manufacturer IDs
                 Make DDR3 manufacturer count parity error non-fatal
                 Strip former manufacturer name in side-by-side output mode
diff --git a/eeprom/decode-dimms b/eeprom/decode-dimms
index b7924a0..6fb4a1c 100755
--- a/eeprom/decode-dimms
+++ b/eeprom/decode-dimms
@@ -1433,6 +1433,25 @@ sub decode_ddr3_sdram($)
 	}
 	printl("Supported CAS Latencies (tCL)", cas_latencies(keys %cas));
 
+# standard DDR3 speeds
+	prints("Timings at Standard Speeds");
+	foreach my $ctime_at_speed (7.5/8, 7.5/7, 1.25, 1.5, 1.875, 2.5) {
+		my $best_cas = 0;
+
+		# Find min CAS latency at this speed
+		for ($ii = 14; $ii >= 0; $ii--) {
+			next unless ($cas_sup & (1 << $ii));
+			if (ceil($taa / $ctime_at_speed) <= $ii + 4) {
+				$best_cas = $ii + 4;
+			}
+		}
+
+		printl_cond($best_cas && $ctime_at_speed >= $ctime,
+			    "tCL-tRCD-tRP-tRAS" . as_ddr(3, $ctime_at_speed),
+			    ddr_core_timings($best_cas, $ctime_at_speed,
+					     $trcd, $trp, $tras));
+	}
+
 # more timing information
 	prints("Timing Parameters");